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[SelectionDAG][RISCV][VE] Rename VP_ASHR->VP_SRA VP_LSHR->VP_SRL. (#93221)
This maintains consistency with the non-VP ISD opcodes.
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6 files changed

+43
-43
lines changed

6 files changed

+43
-43
lines changed

‎llvm/include/llvm/IR/VPIntrinsics.def

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -174,10 +174,10 @@ HELPER_REGISTER_BINARY_INT_VP(vp_add, VP_ADD, Add, ADD)
174174
HELPER_REGISTER_BINARY_INT_VP(vp_and, VP_AND, And, AND)
175175

176176
// llvm.vp.ashr(x,y,mask,vlen)
177-
HELPER_REGISTER_BINARY_INT_VP(vp_ashr, VP_ASHR, AShr, SRA)
177+
HELPER_REGISTER_BINARY_INT_VP(vp_ashr, VP_SRA, AShr, SRA)
178178

179179
// llvm.vp.lshr(x,y,mask,vlen)
180-
HELPER_REGISTER_BINARY_INT_VP(vp_lshr, VP_LSHR, LShr, SRL)
180+
HELPER_REGISTER_BINARY_INT_VP(vp_lshr, VP_SRL, LShr, SRL)
181181

182182
// llvm.vp.mul(x,y,mask,vlen)
183183
HELPER_REGISTER_BINARY_INT_VP(vp_mul, VP_MUL, Mul, MUL)

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -107,9 +107,9 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
107107
case ISD::SIGN_EXTEND_INREG:
108108
Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
109109
case ISD::SRA:
110-
case ISD::VP_ASHR: Res = PromoteIntRes_SRA(N); break;
110+
case ISD::VP_SRA: Res = PromoteIntRes_SRA(N); break;
111111
case ISD::SRL:
112-
case ISD::VP_LSHR: Res = PromoteIntRes_SRL(N); break;
112+
case ISD::VP_SRL: Res = PromoteIntRes_SRL(N); break;
113113
case ISD::VP_TRUNCATE:
114114
case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
115115
case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
@@ -573,7 +573,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
573573
ShAmt);
574574
SDValue Mask = N->getOperand(1);
575575
SDValue EVL = N->getOperand(2);
576-
return DAG.getNode(ISD::VP_LSHR, dl, NVT,
576+
return DAG.getNode(ISD::VP_SRL, dl, NVT,
577577
DAG.getNode(ISD::VP_BSWAP, dl, NVT, Op, Mask, EVL), ShAmt,
578578
Mask, EVL);
579579
}
@@ -601,7 +601,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
601601
DAG.getNode(ISD::BITREVERSE, dl, NVT, Op), ShAmt);
602602
SDValue Mask = N->getOperand(1);
603603
SDValue EVL = N->getOperand(2);
604-
return DAG.getNode(ISD::VP_LSHR, dl, NVT,
604+
return DAG.getNode(ISD::VP_SRL, dl, NVT,
605605
DAG.getNode(ISD::VP_BITREVERSE, dl, NVT, Op, Mask, EVL),
606606
ShAmt, Mask, EVL);
607607
}
@@ -1405,7 +1405,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
14051405
SDValue RHS = N->getOperand(1);
14061406
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
14071407
RHS = ZExtPromotedInteger(RHS);
1408-
if (N->getOpcode() != ISD::VP_ASHR)
1408+
if (N->getOpcode() != ISD::VP_SRA)
14091409
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
14101410
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
14111411
N->getOperand(2), N->getOperand(3));
@@ -1417,7 +1417,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
14171417
SDValue RHS = N->getOperand(1);
14181418
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
14191419
RHS = ZExtPromotedInteger(RHS);
1420-
if (N->getOpcode() != ISD::VP_LSHR)
1420+
if (N->getOpcode() != ISD::VP_SRL)
14211421
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
14221422
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
14231423
N->getOperand(2), N->getOperand(3));
@@ -1513,10 +1513,10 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VPFunnelShift(SDNode *N) {
15131513
Hi = DAG.getNode(ISD::VP_SHL, DL, VT, Hi, HiShift, Mask, EVL);
15141514
Lo = DAG.getVPZeroExtendInReg(Lo, Mask, EVL, DL, OldVT);
15151515
SDValue Res = DAG.getNode(ISD::VP_OR, DL, VT, Hi, Lo, Mask, EVL);
1516-
Res = DAG.getNode(IsFSHR ? ISD::VP_LSHR : ISD::VP_SHL, DL, VT, Res, Amt,
1516+
Res = DAG.getNode(IsFSHR ? ISD::VP_SRL : ISD::VP_SHL, DL, VT, Res, Amt,
15171517
Mask, EVL);
15181518
if (!IsFSHR)
1519-
Res = DAG.getNode(ISD::VP_LSHR, DL, VT, Res, HiShift, Mask, EVL);
1519+
Res = DAG.getNode(ISD::VP_SRL, DL, VT, Res, HiShift, Mask, EVL);
15201520
return Res;
15211521
}
15221522

@@ -2212,7 +2212,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_VP_SIGN_EXTEND(SDNode *N) {
22122212
// FIXME: There is no VP_SIGN_EXTEND_INREG so use a pair of shifts.
22132213
SDValue Shl = DAG.getNode(ISD::VP_SHL, dl, VT, Op, ShAmt, N->getOperand(1),
22142214
N->getOperand(2));
2215-
return DAG.getNode(ISD::VP_ASHR, dl, VT, Shl, ShAmt, N->getOperand(1),
2215+
return DAG.getNode(ISD::VP_SRA, dl, VT, Shl, ShAmt, N->getOperand(1),
22162216
N->getOperand(2));
22172217
}
22182218

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1188,8 +1188,8 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
11881188
case ISD::OR: case ISD::VP_OR:
11891189
case ISD::XOR: case ISD::VP_XOR:
11901190
case ISD::SHL: case ISD::VP_SHL:
1191-
case ISD::SRA: case ISD::VP_ASHR:
1192-
case ISD::SRL: case ISD::VP_LSHR:
1191+
case ISD::SRA: case ISD::VP_SRA:
1192+
case ISD::SRL: case ISD::VP_SRL:
11931193
case ISD::UREM: case ISD::VP_UREM:
11941194
case ISD::SREM: case ISD::VP_SREM:
11951195
case ISD::FREM: case ISD::VP_FREM:
@@ -4235,8 +4235,8 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
42354235
case ISD::SUB: case ISD::VP_SUB:
42364236
case ISD::XOR: case ISD::VP_XOR:
42374237
case ISD::SHL: case ISD::VP_SHL:
4238-
case ISD::SRA: case ISD::VP_ASHR:
4239-
case ISD::SRL: case ISD::VP_LSHR:
4238+
case ISD::SRA: case ISD::VP_SRA:
4239+
case ISD::SRL: case ISD::VP_SRL:
42404240
case ISD::FMINNUM: case ISD::VP_FMINNUM:
42414241
case ISD::FMAXNUM: case ISD::VP_FMAXNUM:
42424242
case ISD::FMINIMUM:

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -7889,7 +7889,7 @@ static SDValue expandVPFunnelShift(SDNode *Node, SelectionDAG &DAG) {
78897889
InvShAmt = DAG.getNode(ISD::VP_SUB, DL, ShVT, BitWidthC, ShAmt, Mask, VL);
78907890
ShX = DAG.getNode(ISD::VP_SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt, Mask,
78917891
VL);
7892-
ShY = DAG.getNode(ISD::VP_LSHR, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt, Mask,
7892+
ShY = DAG.getNode(ISD::VP_SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt, Mask,
78937893
VL);
78947894
} else {
78957895
// fshl: X << (Z % BW) | Y >> 1 >> (BW - 1 - (Z % BW))
@@ -7911,12 +7911,12 @@ static SDValue expandVPFunnelShift(SDNode *Node, SelectionDAG &DAG) {
79117911
SDValue One = DAG.getConstant(1, DL, ShVT);
79127912
if (IsFSHL) {
79137913
ShX = DAG.getNode(ISD::VP_SHL, DL, VT, X, ShAmt, Mask, VL);
7914-
SDValue ShY1 = DAG.getNode(ISD::VP_LSHR, DL, VT, Y, One, Mask, VL);
7915-
ShY = DAG.getNode(ISD::VP_LSHR, DL, VT, ShY1, InvShAmt, Mask, VL);
7914+
SDValue ShY1 = DAG.getNode(ISD::VP_SRL, DL, VT, Y, One, Mask, VL);
7915+
ShY = DAG.getNode(ISD::VP_SRL, DL, VT, ShY1, InvShAmt, Mask, VL);
79167916
} else {
79177917
SDValue ShX1 = DAG.getNode(ISD::VP_SHL, DL, VT, X, One, Mask, VL);
79187918
ShX = DAG.getNode(ISD::VP_SHL, DL, VT, ShX1, InvShAmt, Mask, VL);
7919-
ShY = DAG.getNode(ISD::VP_LSHR, DL, VT, Y, ShAmt, Mask, VL);
7919+
ShY = DAG.getNode(ISD::VP_SRL, DL, VT, Y, ShAmt, Mask, VL);
79207920
}
79217921
}
79227922
return DAG.getNode(ISD::VP_OR, DL, VT, ShX, ShY, Mask, VL);
@@ -8883,21 +8883,21 @@ SDValue TargetLowering::expandVPCTPOP(SDNode *Node, SelectionDAG &DAG) const {
88838883

88848884
// v = v - ((v >> 1) & 0x55555555...)
88858885
Tmp1 = DAG.getNode(ISD::VP_AND, dl, VT,
8886-
DAG.getNode(ISD::VP_LSHR, dl, VT, Op,
8886+
DAG.getNode(ISD::VP_SRL, dl, VT, Op,
88878887
DAG.getConstant(1, dl, ShVT), Mask, VL),
88888888
Mask55, Mask, VL);
88898889
Op = DAG.getNode(ISD::VP_SUB, dl, VT, Op, Tmp1, Mask, VL);
88908890

88918891
// v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
88928892
Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Op, Mask33, Mask, VL);
88938893
Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT,
8894-
DAG.getNode(ISD::VP_LSHR, dl, VT, Op,
8894+
DAG.getNode(ISD::VP_SRL, dl, VT, Op,
88958895
DAG.getConstant(2, dl, ShVT), Mask, VL),
88968896
Mask33, Mask, VL);
88978897
Op = DAG.getNode(ISD::VP_ADD, dl, VT, Tmp2, Tmp3, Mask, VL);
88988898

88998899
// v = (v + (v >> 4)) & 0x0F0F0F0F...
8900-
Tmp4 = DAG.getNode(ISD::VP_LSHR, dl, VT, Op, DAG.getConstant(4, dl, ShVT),
8900+
Tmp4 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(4, dl, ShVT),
89018901
Mask, VL),
89028902
Tmp5 = DAG.getNode(ISD::VP_ADD, dl, VT, Op, Tmp4, Mask, VL);
89038903
Op = DAG.getNode(ISD::VP_AND, dl, VT, Tmp5, Mask0F, Mask, VL);
@@ -8921,8 +8921,8 @@ SDValue TargetLowering::expandVPCTPOP(SDNode *Node, SelectionDAG &DAG) const {
89218921
Mask, VL);
89228922
}
89238923
}
8924-
return DAG.getNode(ISD::VP_LSHR, dl, VT, V,
8925-
DAG.getConstant(Len - 8, dl, ShVT), Mask, VL);
8924+
return DAG.getNode(ISD::VP_SRL, dl, VT, V, DAG.getConstant(Len - 8, dl, ShVT),
8925+
Mask, VL);
89268926
}
89278927

89288928
SDValue TargetLowering::expandCTLZ(SDNode *Node, SelectionDAG &DAG) const {
@@ -8994,7 +8994,7 @@ SDValue TargetLowering::expandVPCTLZ(SDNode *Node, SelectionDAG &DAG) const {
89948994
for (unsigned i = 0; (1U << i) < NumBitsPerElt; ++i) {
89958995
SDValue Tmp = DAG.getConstant(1ULL << i, dl, ShVT);
89968996
Op = DAG.getNode(ISD::VP_OR, dl, VT, Op,
8997-
DAG.getNode(ISD::VP_LSHR, dl, VT, Op, Tmp, Mask, VL), Mask,
8997+
DAG.getNode(ISD::VP_SRL, dl, VT, Op, Tmp, Mask, VL), Mask,
89988998
VL);
89998999
}
90009000
Op = DAG.getNode(ISD::VP_XOR, dl, VT, Op, DAG.getConstant(-1, dl, VT), Mask,
@@ -9323,7 +9323,7 @@ SDValue TargetLowering::expandVPBSWAP(SDNode *N, SelectionDAG &DAG) const {
93239323
case MVT::i16:
93249324
Tmp1 = DAG.getNode(ISD::VP_SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT),
93259325
Mask, EVL);
9326-
Tmp2 = DAG.getNode(ISD::VP_LSHR, dl, VT, Op, DAG.getConstant(8, dl, SHVT),
9326+
Tmp2 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT),
93279327
Mask, EVL);
93289328
return DAG.getNode(ISD::VP_OR, dl, VT, Tmp1, Tmp2, Mask, EVL);
93299329
case MVT::i32:
@@ -9333,11 +9333,11 @@ SDValue TargetLowering::expandVPBSWAP(SDNode *N, SelectionDAG &DAG) const {
93339333
Mask, EVL);
93349334
Tmp3 = DAG.getNode(ISD::VP_SHL, dl, VT, Tmp3, DAG.getConstant(8, dl, SHVT),
93359335
Mask, EVL);
9336-
Tmp2 = DAG.getNode(ISD::VP_LSHR, dl, VT, Op, DAG.getConstant(8, dl, SHVT),
9336+
Tmp2 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT),
93379337
Mask, EVL);
93389338
Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2,
93399339
DAG.getConstant(0xFF00, dl, VT), Mask, EVL);
9340-
Tmp1 = DAG.getNode(ISD::VP_LSHR, dl, VT, Op, DAG.getConstant(24, dl, SHVT),
9340+
Tmp1 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT),
93419341
Mask, EVL);
93429342
Tmp4 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp4, Tmp3, Mask, EVL);
93439343
Tmp2 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp2, Tmp1, Mask, EVL);
@@ -9357,19 +9357,19 @@ SDValue TargetLowering::expandVPBSWAP(SDNode *N, SelectionDAG &DAG) const {
93579357
DAG.getConstant(255ULL << 24, dl, VT), Mask, EVL);
93589358
Tmp5 = DAG.getNode(ISD::VP_SHL, dl, VT, Tmp5, DAG.getConstant(8, dl, SHVT),
93599359
Mask, EVL);
9360-
Tmp4 = DAG.getNode(ISD::VP_LSHR, dl, VT, Op, DAG.getConstant(8, dl, SHVT),
9360+
Tmp4 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT),
93619361
Mask, EVL);
93629362
Tmp4 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp4,
93639363
DAG.getConstant(255ULL << 24, dl, VT), Mask, EVL);
9364-
Tmp3 = DAG.getNode(ISD::VP_LSHR, dl, VT, Op, DAG.getConstant(24, dl, SHVT),
9364+
Tmp3 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT),
93659365
Mask, EVL);
93669366
Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp3,
93679367
DAG.getConstant(255ULL << 16, dl, VT), Mask, EVL);
9368-
Tmp2 = DAG.getNode(ISD::VP_LSHR, dl, VT, Op, DAG.getConstant(40, dl, SHVT),
9368+
Tmp2 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT),
93699369
Mask, EVL);
93709370
Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2,
93719371
DAG.getConstant(255ULL << 8, dl, VT), Mask, EVL);
9372-
Tmp1 = DAG.getNode(ISD::VP_LSHR, dl, VT, Op, DAG.getConstant(56, dl, SHVT),
9372+
Tmp1 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT),
93739373
Mask, EVL);
93749374
Tmp8 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp8, Tmp7, Mask, EVL);
93759375
Tmp6 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp6, Tmp5, Mask, EVL);
@@ -9468,7 +9468,7 @@ SDValue TargetLowering::expandVPBITREVERSE(SDNode *N, SelectionDAG &DAG) const {
94689468
Tmp = (Sz > 8 ? DAG.getNode(ISD::VP_BSWAP, dl, VT, Op, Mask, EVL) : Op);
94699469

94709470
// swap i4: ((V >> 4) & 0x0F) | ((V & 0x0F) << 4)
9471-
Tmp2 = DAG.getNode(ISD::VP_LSHR, dl, VT, Tmp, DAG.getConstant(4, dl, SHVT),
9471+
Tmp2 = DAG.getNode(ISD::VP_SRL, dl, VT, Tmp, DAG.getConstant(4, dl, SHVT),
94729472
Mask, EVL);
94739473
Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2,
94749474
DAG.getConstant(Mask4, dl, VT), Mask, EVL);
@@ -9479,7 +9479,7 @@ SDValue TargetLowering::expandVPBITREVERSE(SDNode *N, SelectionDAG &DAG) const {
94799479
Tmp = DAG.getNode(ISD::VP_OR, dl, VT, Tmp2, Tmp3, Mask, EVL);
94809480

94819481
// swap i2: ((V >> 2) & 0x33) | ((V & 0x33) << 2)
9482-
Tmp2 = DAG.getNode(ISD::VP_LSHR, dl, VT, Tmp, DAG.getConstant(2, dl, SHVT),
9482+
Tmp2 = DAG.getNode(ISD::VP_SRL, dl, VT, Tmp, DAG.getConstant(2, dl, SHVT),
94839483
Mask, EVL);
94849484
Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2,
94859485
DAG.getConstant(Mask2, dl, VT), Mask, EVL);
@@ -9490,7 +9490,7 @@ SDValue TargetLowering::expandVPBITREVERSE(SDNode *N, SelectionDAG &DAG) const {
94909490
Tmp = DAG.getNode(ISD::VP_OR, dl, VT, Tmp2, Tmp3, Mask, EVL);
94919491

94929492
// swap i1: ((V >> 1) & 0x55) | ((V & 0x55) << 1)
9493-
Tmp2 = DAG.getNode(ISD::VP_LSHR, dl, VT, Tmp, DAG.getConstant(1, dl, SHVT),
9493+
Tmp2 = DAG.getNode(ISD::VP_SRL, dl, VT, Tmp, DAG.getConstant(1, dl, SHVT),
94949494
Mask, EVL);
94959495
Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2,
94969496
DAG.getConstant(Mask1, dl, VT), Mask, EVL);

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -688,7 +688,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
688688
ISD::VP_ADD, ISD::VP_SUB, ISD::VP_MUL,
689689
ISD::VP_SDIV, ISD::VP_UDIV, ISD::VP_SREM,
690690
ISD::VP_UREM, ISD::VP_AND, ISD::VP_OR,
691-
ISD::VP_XOR, ISD::VP_ASHR, ISD::VP_LSHR,
691+
ISD::VP_XOR, ISD::VP_SRA, ISD::VP_SRL,
692692
ISD::VP_SHL, ISD::VP_REDUCE_ADD, ISD::VP_REDUCE_AND,
693693
ISD::VP_REDUCE_OR, ISD::VP_REDUCE_XOR, ISD::VP_REDUCE_SMAX,
694694
ISD::VP_REDUCE_SMIN, ISD::VP_REDUCE_UMAX, ISD::VP_REDUCE_UMIN,
@@ -5341,7 +5341,7 @@ RISCVTargetLowering::lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op,
53415341
SDValue Exp;
53425342
// Restore back to original type. Truncation after SRL is to generate vnsrl.
53435343
if (Op->isVPOpcode()) {
5344-
Exp = DAG.getNode(ISD::VP_LSHR, DL, IntVT, Bitcast,
5344+
Exp = DAG.getNode(ISD::VP_SRL, DL, IntVT, Bitcast,
53455345
DAG.getConstant(ShiftAmt, DL, IntVT), Mask, VL);
53465346
Exp = DAG.getVPZExtOrTrunc(DL, VT, Exp, Mask, VL);
53475347
} else {
@@ -5923,9 +5923,9 @@ static unsigned getRISCVVLOp(SDValue Op) {
59235923
case ISD::VP_SELECT:
59245924
case ISD::VP_MERGE:
59255925
return RISCVISD::VMERGE_VL;
5926-
case ISD::VP_ASHR:
5926+
case ISD::VP_SRA:
59275927
return RISCVISD::SRA_VL;
5928-
case ISD::VP_LSHR:
5928+
case ISD::VP_SRL:
59295929
return RISCVISD::SRL_VL;
59305930
case ISD::VP_SQRT:
59315931
return RISCVISD::FSQRT_VL;
@@ -7010,8 +7010,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
70107010
!Subtarget.hasVInstructionsF16()))
70117011
return SplitVPOp(Op, DAG);
70127012
[[fallthrough]];
7013-
case ISD::VP_ASHR:
7014-
case ISD::VP_LSHR:
7013+
case ISD::VP_SRA:
7014+
case ISD::VP_SRL:
70157015
case ISD::VP_SHL:
70167016
return lowerVPOp(Op, DAG);
70177017
case ISD::VP_IS_FPCLASS:

‎llvm/lib/Target/VE/VVPNodes.def

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -99,8 +99,8 @@ ADD_BINARY_VVP_OP_COMPACT(MUL)
9999
ADD_BINARY_VVP_OP_COMPACT(UDIV)
100100
ADD_BINARY_VVP_OP_COMPACT(SDIV)
101101

102-
ADD_BINARY_VVP_OP(VVP_SRA,VP_ASHR,SRA) REGISTER_PACKED(VVP_SRA)
103-
ADD_BINARY_VVP_OP(VVP_SRL,VP_LSHR,SRL) REGISTER_PACKED(VVP_SRL)
102+
ADD_BINARY_VVP_OP(VVP_SRA,VP_SRA,SRA) REGISTER_PACKED(VVP_SRA)
103+
ADD_BINARY_VVP_OP(VVP_SRL,VP_SRL,SRL) REGISTER_PACKED(VVP_SRL)
104104
ADD_BINARY_VVP_OP_COMPACT(SHL) REGISTER_PACKED(VVP_SHL)
105105

106106
ADD_BINARY_VVP_OP_COMPACT(AND) REGISTER_PACKED(VVP_AND)

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