@@ -134,14 +134,12 @@ let Form = MRMSrcMem;
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let SchedRW = [sched.Folded, sched.ReadAfterFold];
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}
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- let Constraints = "$src1 = $dst" in {
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def IMUL16rr : IMulOpRR<Xi16, WriteIMul16Reg>, OpSize16;
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def IMUL32rr : IMulOpRR<Xi32, WriteIMul32Reg>, OpSize32;
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def IMUL64rr : IMulOpRR<Xi64, WriteIMul64Reg>;
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def IMUL16rm : IMulOpRM<Xi16, WriteIMul16Reg>, OpSize16;
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def IMUL32rm : IMulOpRM<Xi32, WriteIMul32Reg>, OpSize32;
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def IMUL64rm : IMulOpRM<Xi64, WriteIMul64Reg>;
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- }
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class IMulOpRI8_R<X86TypeInfo t, X86FoldableSchedWrite sched>
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: BinOpRI8<0x6B, "imul", binop_ndd_args, t, MRMSrcReg,
@@ -547,7 +545,6 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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// These are for the disassembler since 0x82 opcode behaves like 0x80, but
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// not in 64-bit mode.
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let Predicates = [Not64BitMode] in {
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- let Constraints = "$src1 = $dst" in
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def NAME#8ri8 : BinOpRI8_RF<0x82, mnemonic, Xi8, RegMRM>, DisassembleOnly;
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def NAME#8mi8 : BinOpMI8_MF<mnemonic, Xi8, MemMRM>, DisassembleOnly;
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}
@@ -719,7 +716,6 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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// These are for the disassembler since 0x82 opcode behaves like 0x80, but
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// not in 64-bit mode.
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let Predicates = [Not64BitMode] in {
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- let Constraints = "$src1 = $dst" in
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def NAME#8ri8 : BinOpRI8F_RF<0x82, mnemonic, Xi8, RegMRM>, DisassembleOnly;
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def NAME#8mi8 : BinOpMI8F_MF<mnemonic, Xi8, MemMRM>, DisassembleOnly;
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}
@@ -1122,17 +1118,15 @@ defm MULX64 : MulX<Xi64, WriteMULX64>, REX_W;
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//
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// We don't have patterns for these as there is no advantage over ADC for
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// most code.
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- let Constraints = "$src1 = $dst" in {
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- let Form = MRMSrcReg in {
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- def ADCX32rr : BinOpRRF_RF<0xF6, "adcx", Xi32, null_frag>, T8, PD;
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- def ADCX64rr : BinOpRRF_RF<0xF6, "adcx", Xi64, null_frag>, T8, PD;
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- def ADOX32rr : BinOpRRF_RF<0xF6, "adox", Xi32, null_frag>, T8, XS;
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- def ADOX64rr : BinOpRRF_RF<0xF6, "adox", Xi64, null_frag>, T8, XS;
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- }
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- let Form = MRMSrcMem in {
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- def ADCX32rm : BinOpRMF_RF<0xF6, "adcx", Xi32, null_frag>, T8, PD;
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- def ADCX64rm : BinOpRMF_RF<0xF6, "adcx", Xi64, null_frag>, T8, PD;
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- def ADOX32rm : BinOpRMF_RF<0xF6, "adox", Xi32, null_frag>, T8, XS;
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- def ADOX64rm : BinOpRMF_RF<0xF6, "adox", Xi64, null_frag>, T8, XS;
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- }
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+ let Form = MRMSrcReg in {
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+ def ADCX32rr : BinOpRRF_RF<0xF6, "adcx", Xi32, null_frag>, T8, PD;
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+ def ADCX64rr : BinOpRRF_RF<0xF6, "adcx", Xi64, null_frag>, T8, PD;
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+ def ADOX32rr : BinOpRRF_RF<0xF6, "adox", Xi32, null_frag>, T8, XS;
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+ def ADOX64rr : BinOpRRF_RF<0xF6, "adox", Xi64, null_frag>, T8, XS;
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+ }
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+ let Form = MRMSrcMem in {
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+ def ADCX32rm : BinOpRMF_RF<0xF6, "adcx", Xi32, null_frag>, T8, PD;
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+ def ADCX64rm : BinOpRMF_RF<0xF6, "adcx", Xi64, null_frag>, T8, PD;
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+ def ADOX32rm : BinOpRMF_RF<0xF6, "adox", Xi32, null_frag>, T8, XS;
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+ def ADOX64rm : BinOpRMF_RF<0xF6, "adox", Xi64, null_frag>, T8, XS;
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}
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