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MDevereauMDevereau
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[AArch64] Add svboolx2_t and svboolx4_t tuple types
https://reviews.llvm.org/D145505
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‎clang/include/clang/Basic/AArch64SVEACLETypes.def

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@@ -129,6 +129,8 @@ SVE_VECTOR_TYPE("__clang_svfloat64x4_t", "svfloat64x4_t", SveFloat64x4, SveFloat
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SVE_VECTOR_TYPE("__clang_svbfloat16x4_t", "svbfloat16x4_t", SveBFloat16x4, SveBFloat16x4Ty, 32, 16, true, false, true)
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SVE_PREDICATE_TYPE("__SVBool_t", "__SVBool_t", SveBool, SveBoolTy, 16)
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SVE_PREDICATE_TYPE("__clang_svboolx2_t", "svboolx2_t", SveBoolx2, SveBoolx2Ty, 32)
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SVE_PREDICATE_TYPE("__clang_svboolx4_t", "svboolx4_t", SveBoolx4, SveBoolx4Ty, 64)
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SVE_OPAQUE_TYPE("__SVCount_t", "__SVCount_t", SveCount, SveCountTy)
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‎clang/lib/AST/ASTContext.cpp

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@@ -4041,6 +4041,10 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType *Ty) const {
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return SVE_INT_ELTTY(64, 2, false, 4);
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case BuiltinType::SveBool:
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return SVE_ELTTY(BoolTy, 16, 1);
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case BuiltinType::SveBoolx2:
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return SVE_ELTTY(BoolTy, 16, 2);
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case BuiltinType::SveBoolx4:
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return SVE_ELTTY(BoolTy, 16, 4);
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case BuiltinType::SveFloat16:
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return SVE_ELTTY(HalfTy, 8, 1);
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case BuiltinType::SveFloat16x2:

‎clang/lib/AST/Type.cpp

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@@ -2401,6 +2401,8 @@ bool Type::isVLSTBuiltinType() const {
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case BuiltinType::SveFloat64:
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case BuiltinType::SveBFloat16:
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case BuiltinType::SveBool:
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case BuiltinType::SveBoolx2:
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case BuiltinType::SveBoolx4:
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return true;
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default:
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return false;

‎clang/lib/CodeGen/CodeGenTypes.cpp

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@@ -596,6 +596,8 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
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case BuiltinType::SveInt64x4:
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case BuiltinType::SveUint64x4:
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case BuiltinType::SveBool:
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case BuiltinType::SveBoolx2:
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case BuiltinType::SveBoolx4:
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case BuiltinType::SveFloat16:
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case BuiltinType::SveFloat16x2:
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case BuiltinType::SveFloat16x3:

‎clang/test/CodeGen/svboolx2_t.cpp

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@@ -0,0 +1,31 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -emit-llvm -o - %s | FileCheck %s
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// CHECK-LABEL: @_Z3foo10svboolx2_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[ARG_ADDR:%.*]] = alloca <vscale x 32 x i1>, align 2
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// CHECK-NEXT: store <vscale x 32 x i1> [[ARG:%.*]], ptr [[ARG_ADDR]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 32 x i1>, ptr [[ARG_ADDR]], align 2
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// CHECK-NEXT: ret <vscale x 32 x i1> [[TMP0]]
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//
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__clang_svboolx2_t foo(__clang_svboolx2_t arg) { return arg; }
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__clang_svboolx2_t bar();
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// CHECK-LABEL: @_Z4foo2v(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CALL:%.*]] = call <vscale x 32 x i1> @_Z3barv()
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// CHECK-NEXT: ret <vscale x 32 x i1> [[CALL]]
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//
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__clang_svboolx2_t foo2() { return bar(); }
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__clang_svboolx2_t bar2(__clang_svboolx2_t);
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// CHECK-LABEL: @_Z4foo310svboolx2_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[ARG_ADDR:%.*]] = alloca <vscale x 32 x i1>, align 2
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// CHECK-NEXT: store <vscale x 32 x i1> [[ARG:%.*]], ptr [[ARG_ADDR]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 32 x i1>, ptr [[ARG_ADDR]], align 2
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// CHECK-NEXT: [[CALL:%.*]] = call <vscale x 32 x i1> @_Z4bar210svboolx2_t(<vscale x 32 x i1> [[TMP0]])
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// CHECK-NEXT: ret <vscale x 32 x i1> [[CALL]]
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//
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__clang_svboolx2_t foo3(__clang_svboolx2_t arg) { return bar2(arg); }
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‎clang/test/CodeGen/svboolx4_t.cpp

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@@ -0,0 +1,31 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -emit-llvm -o - %s | FileCheck %s
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// CHECK-LABEL: @_Z3foo10svboolx4_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[ARG_ADDR:%.*]] = alloca <vscale x 64 x i1>, align 2
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// CHECK-NEXT: store <vscale x 64 x i1> [[ARG:%.*]], ptr [[ARG_ADDR]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 64 x i1>, ptr [[ARG_ADDR]], align 2
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// CHECK-NEXT: ret <vscale x 64 x i1> [[TMP0]]
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//
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__clang_svboolx4_t foo(__clang_svboolx4_t arg) { return arg; }
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__clang_svboolx4_t bar();
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// CHECK-LABEL: @_Z4foo2v(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CALL:%.*]] = call <vscale x 64 x i1> @_Z3barv()
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// CHECK-NEXT: ret <vscale x 64 x i1> [[CALL]]
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//
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__clang_svboolx4_t foo2() { return bar(); }
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__clang_svboolx4_t bar2(__clang_svboolx4_t);
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// CHECK-LABEL: @_Z4foo310svboolx4_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[ARG_ADDR:%.*]] = alloca <vscale x 64 x i1>, align 2
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// CHECK-NEXT: store <vscale x 64 x i1> [[ARG:%.*]], ptr [[ARG_ADDR]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 64 x i1>, ptr [[ARG_ADDR]], align 2
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// CHECK-NEXT: [[CALL:%.*]] = call <vscale x 64 x i1> @_Z4bar210svboolx4_t(<vscale x 64 x i1> [[TMP0]])
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// CHECK-NEXT: ret <vscale x 64 x i1> [[CALL]]
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//
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__clang_svboolx4_t foo3(__clang_svboolx4_t arg) { return bar2(arg); }
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‎clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp

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Original file line numberDiff line numberDiff line change
@@ -108,3 +108,7 @@ void f46(S<__clang_svbfloat16x2_t>) {}
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void f47(S<__clang_svbfloat16x3_t>) {}
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// CHECK: _Z3f481SI14svbfloat16x4_tE
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void f48(S<__clang_svbfloat16x4_t>) {}
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// CHECK: _Z3f491SI10svboolx2_tE
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void f49(S<__clang_svboolx2_t>) {}
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// CHECK: _Z3f501SI10svboolx4_tE
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void f50(S<__clang_svboolx4_t>) {}

‎clang/utils/TableGen/SveEmitter.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1140,7 +1140,9 @@ void SVEEmitter::createHeader(raw_ostream &OS) {
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OS << "typedef __clang_svfloat16x4_t svfloat16x4_t;\n";
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OS << "typedef __clang_svfloat32x4_t svfloat32x4_t;\n";
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OS << "typedef __clang_svfloat64x4_t svfloat64x4_t;\n";
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OS << "typedef __SVBool_t svbool_t;\n\n";
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OS << "typedef __SVBool_t svbool_t;\n";
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OS << "typedef __clang_svboolx2_t svboolx2_t;\n";
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OS << "typedef __clang_svboolx4_t svboolx4_t;\n\n";
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OS << "typedef __clang_svbfloat16x2_t svbfloat16x2_t;\n";
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OS << "typedef __clang_svbfloat16x3_t svbfloat16x3_t;\n";

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