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[X86] Use MCRegister in more places. NFC (#108682)
1 parent 55ec015 commit a20a973

11 files changed

+97
-99
lines changed

‎llvm/lib/Target/X86/AsmParser/X86Operand.h

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ struct X86Operand final : public MCParsedAsmOperand {
4747
};
4848

4949
struct RegOp {
50-
unsigned RegNo;
50+
MCRegister RegNo;
5151
};
5252

5353
struct PrefOp {
@@ -60,11 +60,11 @@ struct X86Operand final : public MCParsedAsmOperand {
6060
};
6161

6262
struct MemOp {
63-
unsigned SegReg;
63+
MCRegister SegReg;
6464
const MCExpr *Disp;
65-
unsigned BaseReg;
66-
unsigned DefaultBaseReg;
67-
unsigned IndexReg;
65+
MCRegister BaseReg;
66+
MCRegister DefaultBaseReg;
67+
MCRegister IndexReg;
6868
unsigned Scale;
6969
unsigned Size;
7070
unsigned ModeSize;
@@ -186,19 +186,19 @@ struct X86Operand final : public MCParsedAsmOperand {
186186
assert(Kind == Memory && "Invalid access!");
187187
return Mem.Disp;
188188
}
189-
unsigned getMemSegReg() const {
189+
MCRegister getMemSegReg() const {
190190
assert(Kind == Memory && "Invalid access!");
191191
return Mem.SegReg;
192192
}
193-
unsigned getMemBaseReg() const {
193+
MCRegister getMemBaseReg() const {
194194
assert(Kind == Memory && "Invalid access!");
195195
return Mem.BaseReg;
196196
}
197-
unsigned getMemDefaultBaseReg() const {
197+
MCRegister getMemDefaultBaseReg() const {
198198
assert(Kind == Memory && "Invalid access!");
199199
return Mem.DefaultBaseReg;
200200
}
201-
unsigned getMemIndexReg() const {
201+
MCRegister getMemIndexReg() const {
202202
assert(Kind == Memory && "Invalid access!");
203203
return Mem.IndexReg;
204204
}
@@ -600,8 +600,8 @@ struct X86Operand final : public MCParsedAsmOperand {
600600

601601
void addMaskPairOperands(MCInst &Inst, unsigned N) const {
602602
assert(N == 1 && "Invalid number of operands!");
603-
unsigned Reg = getReg();
604-
switch (Reg) {
603+
MCRegister Reg = getReg();
604+
switch (Reg.id()) {
605605
case X86::K0:
606606
case X86::K1:
607607
Reg = X86::K0_K1;
@@ -673,11 +673,11 @@ struct X86Operand final : public MCParsedAsmOperand {
673673
}
674674

675675
static std::unique_ptr<X86Operand>
676-
CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
676+
CreateReg(MCRegister Reg, SMLoc StartLoc, SMLoc EndLoc,
677677
bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
678678
StringRef SymName = StringRef(), void *OpDecl = nullptr) {
679679
auto Res = std::make_unique<X86Operand>(Register, StartLoc, EndLoc);
680-
Res->Reg.RegNo = RegNo;
680+
Res->Reg.RegNo = Reg;
681681
Res->AddressOf = AddressOf;
682682
Res->OffsetOfLoc = OffsetOfLoc;
683683
Res->SymName = SymName;
@@ -718,11 +718,11 @@ struct X86Operand final : public MCParsedAsmOperand {
718718
void *OpDecl = nullptr, unsigned FrontendSize = 0,
719719
bool UseUpRegs = false, bool MaybeDirectBranchDest = true) {
720720
auto Res = std::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
721-
Res->Mem.SegReg = 0;
721+
Res->Mem.SegReg = MCRegister();
722722
Res->Mem.Disp = Disp;
723-
Res->Mem.BaseReg = 0;
724-
Res->Mem.DefaultBaseReg = 0;
725-
Res->Mem.IndexReg = 0;
723+
Res->Mem.BaseReg = MCRegister();
724+
Res->Mem.DefaultBaseReg = MCRegister();
725+
Res->Mem.IndexReg = MCRegister();
726726
Res->Mem.Scale = 1;
727727
Res->Mem.Size = Size;
728728
Res->Mem.ModeSize = ModeSize;
@@ -737,10 +737,10 @@ struct X86Operand final : public MCParsedAsmOperand {
737737

738738
/// Create a generalized memory operand.
739739
static std::unique_ptr<X86Operand>
740-
CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
741-
unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
742-
SMLoc EndLoc, unsigned Size = 0,
743-
unsigned DefaultBaseReg = X86::NoRegister,
740+
CreateMem(unsigned ModeSize, MCRegister SegReg, const MCExpr *Disp,
741+
MCRegister BaseReg, MCRegister IndexReg, unsigned Scale,
742+
SMLoc StartLoc, SMLoc EndLoc, unsigned Size = 0,
743+
MCRegister DefaultBaseReg = MCRegister(),
744744
StringRef SymName = StringRef(), void *OpDecl = nullptr,
745745
unsigned FrontendSize = 0, bool UseUpRegs = false,
746746
bool MaybeDirectBranchDest = true) {

‎llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -516,8 +516,7 @@ void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
516516

517517
void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
518518
raw_ostream &OS) {
519-
const MCOperand &Op = MI->getOperand(OpNo);
520-
unsigned Reg = Op.getReg();
519+
MCRegister Reg = MI->getOperand(OpNo).getReg();
521520
// Override the default printing to print st(0) instead st.
522521
if (Reg == X86::ST0)
523522
markup(OS, Markup::Register) << "%st(0)";

‎llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -262,7 +262,7 @@ static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII) {
262262
if (MemoryOperand < 0)
263263
return false;
264264
unsigned BaseRegNum = MemoryOperand + CurOp + X86::AddrBaseReg;
265-
unsigned BaseReg = MI.getOperand(BaseRegNum).getReg();
265+
MCRegister BaseReg = MI.getOperand(BaseRegNum).getReg();
266266
return (BaseReg == X86::RIP);
267267
}
268268

@@ -302,7 +302,7 @@ uint8_t X86AsmBackend::determinePaddingPrefix(const MCInst &Inst) const {
302302
if (MemoryOperand != -1)
303303
MemoryOperand += X86II::getOperandBias(Desc);
304304

305-
unsigned SegmentReg = 0;
305+
MCRegister SegmentReg;
306306
if (MemoryOperand >= 0) {
307307
// Check for explicit segment override on memory operand.
308308
SegmentReg = Inst.getOperand(MemoryOperand + X86::AddrSegmentReg).getReg();
@@ -338,7 +338,7 @@ uint8_t X86AsmBackend::determinePaddingPrefix(const MCInst &Inst) const {
338338

339339
if (MemoryOperand >= 0) {
340340
unsigned BaseRegNum = MemoryOperand + X86::AddrBaseReg;
341-
unsigned BaseReg = Inst.getOperand(BaseRegNum).getReg();
341+
MCRegister BaseReg = Inst.getOperand(BaseRegNum).getReg();
342342
if (BaseReg == X86::ESP || BaseReg == X86::EBP)
343343
return X86::SS_Encoding;
344344
}

‎llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -329,8 +329,8 @@ enum EncodingOfSegmentOverridePrefix : uint8_t {
329329
/// Given a segment register, return the encoding of the segment override
330330
/// prefix for it.
331331
inline EncodingOfSegmentOverridePrefix
332-
getSegmentOverridePrefixForReg(unsigned Reg) {
333-
switch (Reg) {
332+
getSegmentOverridePrefixForReg(MCRegister Reg) {
333+
switch (Reg.id()) {
334334
default:
335335
llvm_unreachable("Unknown segment register!");
336336
case X86::CS:
@@ -1156,52 +1156,52 @@ inline int getMemoryOperandNo(uint64_t TSFlags) {
11561156
}
11571157

11581158
/// \returns true if the register is a XMM.
1159-
inline bool isXMMReg(unsigned RegNo) {
1159+
inline bool isXMMReg(MCRegister Reg) {
11601160
static_assert(X86::XMM15 - X86::XMM0 == 15,
11611161
"XMM0-15 registers are not continuous");
11621162
static_assert(X86::XMM31 - X86::XMM16 == 15,
11631163
"XMM16-31 registers are not continuous");
1164-
return (RegNo >= X86::XMM0 && RegNo <= X86::XMM15) ||
1165-
(RegNo >= X86::XMM16 && RegNo <= X86::XMM31);
1164+
return (Reg >= X86::XMM0 && Reg <= X86::XMM15) ||
1165+
(Reg >= X86::XMM16 && Reg <= X86::XMM31);
11661166
}
11671167

11681168
/// \returns true if the register is a YMM.
1169-
inline bool isYMMReg(unsigned RegNo) {
1169+
inline bool isYMMReg(MCRegister Reg) {
11701170
static_assert(X86::YMM15 - X86::YMM0 == 15,
11711171
"YMM0-15 registers are not continuous");
11721172
static_assert(X86::YMM31 - X86::YMM16 == 15,
11731173
"YMM16-31 registers are not continuous");
1174-
return (RegNo >= X86::YMM0 && RegNo <= X86::YMM15) ||
1175-
(RegNo >= X86::YMM16 && RegNo <= X86::YMM31);
1174+
return (Reg >= X86::YMM0 && Reg <= X86::YMM15) ||
1175+
(Reg >= X86::YMM16 && Reg <= X86::YMM31);
11761176
}
11771177

11781178
/// \returns true if the register is a ZMM.
1179-
inline bool isZMMReg(unsigned RegNo) {
1179+
inline bool isZMMReg(MCRegister Reg) {
11801180
static_assert(X86::ZMM31 - X86::ZMM0 == 31,
11811181
"ZMM registers are not continuous");
1182-
return RegNo >= X86::ZMM0 && RegNo <= X86::ZMM31;
1182+
return Reg >= X86::ZMM0 && Reg <= X86::ZMM31;
11831183
}
11841184

1185-
/// \returns true if \p RegNo is an apx extended register.
1186-
inline bool isApxExtendedReg(unsigned RegNo) {
1185+
/// \returns true if \p Reg is an apx extended register.
1186+
inline bool isApxExtendedReg(MCRegister Reg) {
11871187
static_assert(X86::R31WH - X86::R16 == 95, "EGPRs are not continuous");
1188-
return RegNo >= X86::R16 && RegNo <= X86::R31WH;
1188+
return Reg >= X86::R16 && Reg <= X86::R31WH;
11891189
}
11901190

11911191
/// \returns true if the MachineOperand is a x86-64 extended (r8 or
11921192
/// higher) register, e.g. r8, xmm8, xmm13, etc.
1193-
inline bool isX86_64ExtendedReg(unsigned RegNo) {
1194-
if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM15) ||
1195-
(RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
1196-
(RegNo >= X86::YMM8 && RegNo <= X86::YMM15) ||
1197-
(RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
1198-
(RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
1193+
inline bool isX86_64ExtendedReg(MCRegister Reg) {
1194+
if ((Reg >= X86::XMM8 && Reg <= X86::XMM15) ||
1195+
(Reg >= X86::XMM16 && Reg <= X86::XMM31) ||
1196+
(Reg >= X86::YMM8 && Reg <= X86::YMM15) ||
1197+
(Reg >= X86::YMM16 && Reg <= X86::YMM31) ||
1198+
(Reg >= X86::ZMM8 && Reg <= X86::ZMM31))
11991199
return true;
12001200

1201-
if (isApxExtendedReg(RegNo))
1201+
if (isApxExtendedReg(Reg))
12021202
return true;
12031203

1204-
switch (RegNo) {
1204+
switch (Reg.id()) {
12051205
default:
12061206
break;
12071207
case X86::R8:
@@ -1299,15 +1299,15 @@ inline bool canUseApxExtendedReg(const MCInstrDesc &Desc) {
12991299

13001300
/// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher)
13011301
/// registers, e.g. zmm21, etc.
1302-
static inline bool is32ExtendedReg(unsigned RegNo) {
1303-
return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
1304-
(RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
1305-
(RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
1302+
static inline bool is32ExtendedReg(MCRegister Reg) {
1303+
return ((Reg >= X86::XMM16 && Reg <= X86::XMM31) ||
1304+
(Reg >= X86::YMM16 && Reg <= X86::YMM31) ||
1305+
(Reg >= X86::ZMM16 && Reg <= X86::ZMM31));
13061306
}
13071307

1308-
inline bool isX86_64NonExtLowByteReg(unsigned reg) {
1309-
return (reg == X86::SPL || reg == X86::BPL || reg == X86::SIL ||
1310-
reg == X86::DIL);
1308+
inline bool isX86_64NonExtLowByteReg(MCRegister Reg) {
1309+
return (Reg == X86::SPL || Reg == X86::BPL || Reg == X86::SIL ||
1310+
Reg == X86::DIL);
13111311
}
13121312

13131313
/// \returns true if this is a masked instruction.
@@ -1321,15 +1321,15 @@ inline bool isKMergeMasked(uint64_t TSFlags) {
13211321
}
13221322

13231323
/// \returns true if the intruction needs a SIB.
1324-
inline bool needSIB(unsigned BaseReg, unsigned IndexReg, bool In64BitMode) {
1324+
inline bool needSIB(MCRegister BaseReg, MCRegister IndexReg, bool In64BitMode) {
13251325
// The SIB byte must be used if there is an index register.
13261326
if (IndexReg)
13271327
return true;
13281328

13291329
// The SIB byte must be used if the base is ESP/RSP/R12/R20/R28, all of
13301330
// which encode to an R/M value of 4, which indicates that a SIB byte is
13311331
// present.
1332-
switch (BaseReg) {
1332+
switch (BaseReg.id()) {
13331333
default:
13341334
// If there is no base register and we're in 64-bit mode, we need a SIB
13351335
// byte to emit an addr that is just 'disp32' (the non-RIP relative form).

‎llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -329,7 +329,7 @@ bool X86::optimizeINCDEC(MCInst &MI, bool In64BitMode) {
329329
return true;
330330
}
331331

332-
static bool isARegister(unsigned Reg) {
332+
static bool isARegister(MCRegister Reg) {
333333
return Reg == X86::AL || Reg == X86::AX || Reg == X86::EAX || Reg == X86::RAX;
334334
}
335335

@@ -364,7 +364,7 @@ bool X86::optimizeMOV(MCInst &MI, bool In64BitMode) {
364364
unsigned RegOp = IsStore ? 0 : 5;
365365
unsigned AddrOp = AddrBase + 3;
366366
// Check whether the destination register can be fixed.
367-
unsigned Reg = MI.getOperand(RegOp).getReg();
367+
MCRegister Reg = MI.getOperand(RegOp).getReg();
368368
if (!isARegister(Reg))
369369
return false;
370370
// Check whether this is an absolute address.
@@ -436,7 +436,7 @@ static bool optimizeToFixedRegisterForm(MCInst &MI) {
436436
FROM_TO(XOR64ri32, XOR64i32)
437437
}
438438
// Check whether the destination register can be fixed.
439-
unsigned Reg = MI.getOperand(0).getReg();
439+
MCRegister Reg = MI.getOperand(0).getReg();
440440
if (!isARegister(Reg))
441441
return false;
442442

‎llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -223,22 +223,22 @@ using namespace llvm;
223223
CASE_AVX_INS_COMMON(Inst##SD4, , mr_Int) \
224224
CASE_AVX_INS_COMMON(Inst##SS4, , mr_Int)
225225

226-
static unsigned getVectorRegSize(unsigned RegNo) {
227-
if (X86II::isZMMReg(RegNo))
226+
static unsigned getVectorRegSize(MCRegister Reg) {
227+
if (X86II::isZMMReg(Reg))
228228
return 512;
229-
if (X86II::isYMMReg(RegNo))
229+
if (X86II::isYMMReg(Reg))
230230
return 256;
231-
if (X86II::isXMMReg(RegNo))
231+
if (X86II::isXMMReg(Reg))
232232
return 128;
233-
if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
233+
if (Reg >= X86::MM0 && Reg <= X86::MM7)
234234
return 64;
235235

236236
llvm_unreachable("Unknown vector reg!");
237237
}
238238

239239
static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize,
240240
unsigned OperandIndex) {
241-
unsigned OpReg = MI->getOperand(OperandIndex).getReg();
241+
MCRegister OpReg = MI->getOperand(OperandIndex).getReg();
242242
return getVectorRegSize(OpReg) / ScalarSize;
243243
}
244244

‎llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -487,8 +487,7 @@ void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
487487

488488
void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
489489
raw_ostream &OS) {
490-
const MCOperand &Op = MI->getOperand(OpNo);
491-
unsigned Reg = Op.getReg();
490+
MCRegister Reg = MI->getOperand(OpNo).getReg();
492491
// Override the default printing to print st(0) instead st.
493492
if (Reg == X86::ST0)
494493
OS << "st(0)";

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