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AMDGPU: Replace amdgpu-no-agpr with amdgpu-agpr-alloc (#129893)
This performs the minimal replacment of amdgpu-no-agpr to amdgpu-agpr-alloc=0. Most of the test diffs are due to the new attribute sorting later alphabetically. We could do better by trying to perform range merging in the attributor, and trying to pick non-0 values.
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‎llvm/docs/AMDGPUUsage.rst

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1698,11 +1698,6 @@ The AMDGPU backend supports the following LLVM IR attributes.
16981698
``amdgpu_max_num_work_groups`` CLANG attribute [CLANG-ATTR]_. Clang only
16991699
emits this attribute when all the three numbers are >= 1.
17001700

1701-
"amdgpu-no-agpr" Indicates the function will not require allocating AGPRs. This is only
1702-
relevant on subtargets with AGPRs. The behavior is undefined if a
1703-
function which requires AGPRs is reached through any function marked
1704-
with this attribute.
1705-
17061701
"amdgpu-hidden-argument" This attribute is used internally by the backend to mark function arguments
17071702
as hidden. Hidden arguments are managed by the compiler and are not part of
17081703
the explicit arguments supplied by the user.
@@ -1721,7 +1716,7 @@ The AMDGPU backend supports the following LLVM IR attributes.
17211716
The behavior is undefined if a function which requires more AGPRs than the
17221717
lower bound is reached through any function marked with a higher value of this
17231718
attribute. A minimum value of 0 indicates the function does not require
1724-
any AGPRs. A minimum of 0 is equivalent to "amdgpu-no-agpr".
1719+
any AGPRs.
17251720

17261721
This is only relevant on targets with AGPRs which support accum_offset (gfx90a+).
17271722

‎llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1235,6 +1235,8 @@ static bool inlineAsmUsesAGPRs(const InlineAsm *IA) {
12351235
return false;
12361236
}
12371237

1238+
// TODO: Migrate to range merge of amdgpu-agpr-alloc.
1239+
// FIXME: Why is this using Attribute::NoUnwind?
12381240
struct AAAMDGPUNoAGPR
12391241
: public IRAttribute<Attribute::NoUnwind,
12401242
StateWrapper<BooleanState, AbstractAttribute>,
@@ -1250,7 +1252,10 @@ struct AAAMDGPUNoAGPR
12501252

12511253
void initialize(Attributor &A) override {
12521254
Function *F = getAssociatedFunction();
1253-
if (F->hasFnAttribute("amdgpu-no-agpr"))
1255+
auto [MinNumAGPR, MaxNumAGPR] =
1256+
AMDGPU::getIntegerPairAttribute(*F, "amdgpu-agpr-alloc", {~0u, ~0u},
1257+
/*OnlyFirstRequired=*/true);
1258+
if (MinNumAGPR == 0)
12541259
indicateOptimisticFixpoint();
12551260
}
12561261

@@ -1297,7 +1302,7 @@ struct AAAMDGPUNoAGPR
12971302
return ChangeStatus::UNCHANGED;
12981303
LLVMContext &Ctx = getAssociatedFunction()->getContext();
12991304
return A.manifestAttrs(getIRPosition(),
1300-
{Attribute::get(Ctx, "amdgpu-no-agpr")});
1305+
{Attribute::get(Ctx, "amdgpu-agpr-alloc", "0")});
13011306
}
13021307

13031308
const std::string getName() const override { return "AAAMDGPUNoAGPR"; }

‎llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -780,5 +780,8 @@ bool SIMachineFunctionInfo::initializeBaseYamlFields(
780780
}
781781

782782
bool SIMachineFunctionInfo::mayUseAGPRs(const Function &F) const {
783-
return !F.hasFnAttribute("amdgpu-no-agpr");
783+
auto [MinNumAGPR, MaxNumAGPR] =
784+
AMDGPU::getIntegerPairAttribute(F, "amdgpu-agpr-alloc", {~0u, ~0u},
785+
/*OnlyFirstRequired=*/true);
786+
return MinNumAGPR != 0u;
784787
}

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -571,7 +571,6 @@ MCRegister SIRegisterInfo::reservedPrivateSegmentBufferReg(
571571

572572
std::pair<unsigned, unsigned>
573573
SIRegisterInfo::getMaxNumVectorRegs(const MachineFunction &MF) const {
574-
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
575574
const unsigned MaxVectorRegs = ST.getMaxNumVGPRs(MF);
576575

577576
unsigned MaxNumVGPRs = MaxVectorRegs;
@@ -592,7 +591,6 @@ SIRegisterInfo::getMaxNumVectorRegs(const MachineFunction &MF) const {
592591

593592
const std::pair<unsigned, unsigned> DefaultNumAGPR = {~0u, ~0u};
594593

595-
// TODO: Replace amdgpu-no-agpr with amdgpu-agpr-alloc=0
596594
// TODO: Move this logic into subtarget on IR function
597595
//
598596
// TODO: The lower bound should probably force the number of required
@@ -603,11 +601,7 @@ SIRegisterInfo::getMaxNumVectorRegs(const MachineFunction &MF) const {
603601

604602
if (MinNumAGPRs == DefaultNumAGPR.first) {
605603
// Default to splitting half the registers if AGPRs are required.
606-
607-
if (MFI->mayNeedAGPRs())
608-
MinNumAGPRs = MaxNumAGPRs = MaxVectorRegs / 2;
609-
else
610-
MinNumAGPRs = 0;
604+
MinNumAGPRs = MaxNumAGPRs = MaxVectorRegs / 2;
611605
} else {
612606
// Align to accum_offset's allocation granularity.
613607
MinNumAGPRs = alignTo(MinNumAGPRs, 4);

‎llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -233,8 +233,8 @@ attributes #1 = { nounwind }
233233
; AKF_HSA: attributes #[[ATTR1]] = { nounwind }
234234
;.
235235
; ATTRIBUTOR_HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
236-
; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
237-
; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
236+
; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
237+
; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
238238
;.
239239
; AKF_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
240240
;.

‎llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,6 @@ define void @no_free_vgprs_at_agpr_to_agpr_copy(float %v0, float %v1) #0 {
1717
declare <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float, float, <16 x float>, i32 immarg, i32 immarg, i32 immarg) #1
1818
declare noundef i32 @llvm.amdgcn.workitem.id.x() #2
1919

20-
attributes #0 = { "amdgpu-no-agpr" "amdgpu-waves-per-eu"="6,6" }
20+
attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-waves-per-eu"="6,6" }
2121
attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
2222
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

‎llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1144,6 +1144,6 @@ declare i32 @llvm.amdgcn.workitem.id.x() #2
11441144
attributes #0 = { "amdgpu-waves-per-eu"="6,6" }
11451145
attributes #1 = { convergent nounwind readnone willreturn }
11461146
attributes #2 = { nounwind readnone willreturn }
1147-
attributes #3 = { "amdgpu-waves-per-eu"="7,7" "amdgpu-no-agpr" }
1147+
attributes #3 = { "amdgpu-waves-per-eu"="7,7" "amdgpu-agpr-alloc"="0" }
11481148
attributes #4 = { "amdgpu-waves-per-eu"="6,6" "amdgpu-flat-work-group-size"="1024,1024" }
1149-
attributes #5 = { "amdgpu-waves-per-eu"="6,6" "amdgpu-no-agpr" }
1149+
attributes #5 = { "amdgpu-waves-per-eu"="6,6" "amdgpu-agpr-alloc"="0" }

‎llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -252,13 +252,13 @@ define amdgpu_kernel void @indirect_calls_none_agpr(i1 %cond) {
252252
}
253253

254254

255-
attributes #0 = { "amdgpu-no-agpr" }
255+
attributes #0 = { "amdgpu-agpr-alloc"="0" }
256256
;.
257257
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
258-
; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
258+
; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
259259
; CHECK: attributes #[[ATTR2]] = { "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
260260
; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx90a" }
261261
; CHECK: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx90a" }
262262
; CHECK: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "target-cpu"="gfx90a" }
263-
; CHECK: attributes #[[ATTR6]] = { "amdgpu-no-agpr" }
263+
; CHECK: attributes #[[ATTR6]] = { "amdgpu-agpr-alloc"="0" }
264264
;.

‎llvm/test/CodeGen/AMDGPU/amdgpu-no-agprs-violations.ll

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefixes=CHECK,GFX908 %s
22
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s 2> %t.err | FileCheck -check-prefixes=CHECK,GFX90A %s
3-
; RUN: FileCheck -check-prefix=ERR < %t.err %s
3+
; RUN: FileCheck --implicit-check-not=error -check-prefix=ERR < %t.err %s
44

55
; Test undefined behavior where a function ends up needing AGPRs that
66
; was marked with "amdgpu-agpr-alloc="="0". There should be no asserts.
@@ -9,7 +9,6 @@
99

1010
; ERR: error: <unknown>:0:0: no registers from class available to allocate in function 'kernel_illegal_agpr_use_asm'
1111
; ERR: error: <unknown>:0:0: no registers from class available to allocate in function 'func_illegal_agpr_use_asm'
12-
; ERR: error: <unknown>:0:0: no registers from class available to allocate in function 'kernel_calls_mfma.f32.32x32x1f32'
1312

1413
; CHECK: {{^}}kernel_illegal_agpr_use_asm:
1514
; CHECK: ; use a0
@@ -32,14 +31,16 @@ define void @func_illegal_agpr_use_asm() #0 {
3231
}
3332

3433
; CHECK-LABEL: {{^}}kernel_calls_mfma.f32.32x32x1f32:
35-
; CHECK: v_accvgpr_write_b32
34+
; GFX908: v_accvgpr_write_b32
35+
; GFX90A-NOT: v_accvgpr_write_b32
3636

3737
; GFX908: NumVgprs: 5
38-
; GFX90A: NumVgprs: 36
39-
; CHECK: NumAgprs: 32
38+
; GFX908: NumAgprs: 32
39+
; GFX90A: NumVgprs: 35
40+
; GFX90A: NumAgprs: 0
4041

4142
; GFX908: TotalNumVgprs: 32
42-
; GFX90A: TotalNumVgprs: 68
43+
; GFX90A: TotalNumVgprs: 35
4344
define amdgpu_kernel void @kernel_calls_mfma.f32.32x32x1f32(ptr addrspace(1) %out, float %a, float %b, <32 x float> %c) #0 {
4445
%result = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %a, float %b, <32 x float> %c, i32 0, i32 0, i32 0)
4546
store <32 x float> %result, ptr addrspace(1) %out

‎llvm/test/CodeGen/AMDGPU/amdgpu-num-agpr.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ define amdgpu_kernel void @min_num_agpr_0_0__amdgpu_no_agpr() #0 {
1515
ret void
1616
}
1717

18-
attributes #0 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-agpr-alloc"="0,0" "amdgpu-no-agpr" }
18+
attributes #0 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-agpr-alloc"="0,0" }
1919

2020
; Check parse of single entry 0
2121

@@ -26,16 +26,16 @@ define amdgpu_kernel void @min_num_agpr_0__amdgpu_no_agpr() #1 {
2626
ret void
2727
}
2828

29-
attributes #1 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-agpr-alloc"="0" "amdgpu-no-agpr" }
29+
attributes #1 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-agpr-alloc"="0" }
3030

3131

3232
; Undefined use
33-
define amdgpu_kernel void @min_num_agpr_1_1__amdgpu_no_agpr() #2 {
33+
define amdgpu_kernel void @min_num_agpr_1_1() #2 {
3434
call void asm sideeffect "; clobber $0","~{a0}"(), !srcloc !{i32 3}
3535
ret void
3636
}
3737

38-
attributes #2 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-agpr-alloc"="1,1" "amdgpu-no-agpr" }
38+
attributes #2 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-agpr-alloc"="1,1" }
3939

4040
; Check parse of single entry 4, interpreted as the minimum. Total budget is 64.
4141
; WARN: warning: <unknown>:0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'min_num_agpr_4__amdgpu_no_agpr': desired occupancy was 8, final occupancy is 7
@@ -48,7 +48,7 @@ define amdgpu_kernel void @min_num_agpr_4__amdgpu_no_agpr() #3 {
4848
ret void
4949
}
5050

51-
attributes #3 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-agpr-alloc"="4" "amdgpu-no-agpr" }
51+
attributes #3 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-agpr-alloc"="4" }
5252

5353

5454
; Allocation granularity requires rounding this to use 4 AGPRs, so the
@@ -79,7 +79,7 @@ define amdgpu_kernel void @min_num_agpr_64_64__amdgpu_no_agpr() #5 {
7979
ret void
8080
}
8181

82-
attributes #5 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-agpr-alloc"="64,64" "amdgpu-no-agpr" }
82+
attributes #5 = { "amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64" "amdgpu-agpr-alloc"="64,64" }
8383

8484
; No free VGPRs
8585
; WARN: warning: inline asm clobber list contains reserved registers: v0 at line 7

‎llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,4 +70,4 @@ define amdgpu_kernel void @amdhsa_kernarg_preload_1_implicit_2(i32 inreg) #0 { r
7070

7171
define amdgpu_kernel void @amdhsa_kernarg_preload_0_implicit_2(i32) #0 { ret void }
7272

73-
attributes #0 = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
73+
attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }

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