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broxigarchenbroxigarchen
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check for vgpr16 putting into vgpr32 case in v2s lowering
1 parent cd6c4b6 commit a245abd

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3 files changed

+611
-259
lines changed

3 files changed

+611
-259
lines changed

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 42 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -7235,24 +7235,44 @@ bool SIInstrWorklist::isDeferred(MachineInstr *MI) {
72357235
return DeferredList.contains(MI);
72367236
}
72377237

7238-
// 16bit SALU use sgpr32. If a 16bit SALU get lowered to VALU in true16 mode,
7239-
// sgpr32 is replaced to vgpr32 which is illegal in t16 inst. Need to add
7240-
// subreg access properly. This can be removed after we have sgpr16 in place
7241-
void SIInstrInfo::legalizeOperandsVALUt16(MachineInstr &Inst,
7238+
// legalize operand between 16bit and 32bit registers in v2s copy
7239+
// lowering (change spgr to vgpr).
7240+
// This is mainly caused by 16bit SALU and 16bit VALU using reg with different
7241+
// size. Need to legalize the size of the operands during the vgpr lowering
7242+
// chain. This can be removed after we have sgpr16 in place
7243+
void SIInstrInfo::legalizeOperandsVALUt16(MachineInstr &MI,
72427244
MachineRegisterInfo &MRI) const {
7243-
unsigned Opcode = Inst.getOpcode();
7244-
if (!AMDGPU::isTrue16Inst(Opcode) || !ST.useRealTrue16Insts())
7245+
if (!ST.useRealTrue16Insts())
72457246
return;
72467247

7247-
for (MachineOperand &Op : Inst.explicit_operands()) {
7248+
unsigned Opcode = MI.getOpcode();
7249+
MachineBasicBlock *MBB = MI.getParent();
7250+
7251+
// legalize operands and check for size mismatch
7252+
for (MachineOperand &Op : MI.explicit_operands()) {
72487253
unsigned OpIdx = Op.getOperandNo();
72497254
if (!OpIdx)
72507255
continue;
7251-
if (Op.isReg() && RI.isVGPR(MRI, Op.getReg())) {
7256+
if (Op.isReg() && Op.getReg().isVirtual() && RI.isVGPR(MRI, Op.getReg())) {
72527257
unsigned RCID = get(Opcode).operands()[OpIdx].RegClass;
7253-
const TargetRegisterClass *RC = RI.getRegClass(RCID);
7254-
if (RI.getRegSizeInBits(*RC) == 16) {
7258+
const TargetRegisterClass *ExpectedRC = RI.getRegClass(RCID);
7259+
const TargetRegisterClass *RC = MRI.getRegClass(Op.getReg());
7260+
if (32 == RI.getRegSizeInBits(*RC) &&
7261+
16 == RI.getRegSizeInBits(*ExpectedRC)) {
72557262
Op.setSubReg(AMDGPU::lo16);
7263+
} else if (16 == RI.getRegSizeInBits(*RC) &&
7264+
32 == RI.getRegSizeInBits(*ExpectedRC)) {
7265+
const DebugLoc &DL = MI.getDebugLoc();
7266+
Register NewDstReg =
7267+
MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
7268+
Register Undef = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
7269+
BuildMI(*MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), Undef);
7270+
BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDstReg)
7271+
.addReg(Op.getReg())
7272+
.addImm(AMDGPU::lo16)
7273+
.addReg(Undef)
7274+
.addImm(AMDGPU::hi16);
7275+
Op.setReg(NewDstReg);
72567276
}
72577277
}
72587278
}
@@ -7793,8 +7813,19 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
77937813
.add(Inst.getOperand(1))
77947814
.add(MachineOperand::CreateImm(AMDGPU::lo16));
77957815
Inst.eraseFromParent();
7796-
77977816
MRI.replaceRegWith(DstReg, NewDstReg);
7817+
// legalize useMI with mismatched size
7818+
for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
7819+
E = MRI.use_end();
7820+
I != E; ++I) {
7821+
MachineInstr &UseMI = *I->getParent();
7822+
unsigned UseMIOpcode = UseMI.getOpcode();
7823+
if (AMDGPU::isTrue16Inst(UseMIOpcode) &&
7824+
(16 ==
7825+
RI.getRegSizeInBits(*getOpRegClass(UseMI, I.getOperandNo())))) {
7826+
I->setSubReg(AMDGPU::lo16);
7827+
}
7828+
}
77987829
addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
77997830
return;
78007831
}

‎llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,72 @@ body: |
5454
%4:vgpr_16 = V_CVT_F16_U16_t16_e64 0, %3:sreg_32, 0, 0, 0, implicit $mode, implicit $exec
5555
...
5656

57+
---
58+
name: salu16_usedby_salu32
59+
body: |
60+
bb.0:
61+
; GCN-LABEL: name: salu16_usedby_salu32
62+
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
63+
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
64+
; GCN-NEXT: [[V_TRUNC_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_TRUNC_F16_t16_e64 0, [[DEF]].lo16, 0, 0, 0, implicit $mode, implicit $exec
65+
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
66+
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_TRUNC_F16_t16_e64_]], %subreg.lo16, [[DEF2]], %subreg.hi16
67+
; GCN-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[REG_SEQUENCE]], [[DEF]], implicit $exec
68+
%0:vgpr_32 = IMPLICIT_DEF
69+
%1:sreg_32 = COPY %0:vgpr_32
70+
%2:sreg_32 = S_TRUNC_F16 %1:sreg_32, implicit $mode
71+
%3:sreg_32 = S_XOR_B32 %2:sreg_32, %1:sreg_32, implicit-def $scc
72+
...
73+
74+
---
75+
name: salu32_usedby_salu16
76+
body: |
77+
bb.0:
78+
; GCN-LABEL: name: salu32_usedby_salu16
79+
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
80+
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
81+
; GCN-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[DEF]], [[DEF]], implicit $exec
82+
; GCN-NEXT: [[V_TRUNC_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_TRUNC_F16_t16_e64 0, [[V_XOR_B32_e64_]].lo16, 0, 0, 0, implicit $mode, implicit $exec
83+
%0:vgpr_32 = IMPLICIT_DEF
84+
%1:sreg_32 = COPY %0:vgpr_32
85+
%2:sreg_32 = S_XOR_B32 %1:sreg_32, %1:sreg_32, implicit-def $scc
86+
%3:sreg_32 = S_TRUNC_F16 %2:sreg_32, implicit $mode
87+
...
88+
89+
---
90+
name: sgpr16_to_spgr32
91+
body: |
92+
bb.0:
93+
; GCN-LABEL: name: sgpr16_to_spgr32
94+
; GCN: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
95+
; GCN-NEXT: [[DEF1:%[0-9]+]]:sgpr_lo16 = IMPLICIT_DEF
96+
; GCN-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:vgpr_32 = SUBREG_TO_REG 0, [[DEF]], %subreg.lo16
97+
; GCN-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:vgpr_32 = SUBREG_TO_REG 0, [[DEF]], %subreg.lo16
98+
; GCN-NEXT: [[V_FMAC_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_FMAC_F16_t16_e64 0, [[SUBREG_TO_REG1]].lo16, 0, [[SUBREG_TO_REG1]].lo16, 0, [[SUBREG_TO_REG]].lo16, 0, 0, 0, implicit $mode, implicit $exec
99+
%0:vgpr_16 = IMPLICIT_DEF
100+
%1:sgpr_lo16 = COPY %0:vgpr_16
101+
%2:sreg_32 = COPY %0:vgpr_16
102+
%3:sreg_32 = COPY %1:sgpr_lo16
103+
%4:sreg_32 = S_FMAC_F16 %3:sreg_32, %3:sreg_32, %2:sreg_32, implicit $mode
104+
...
105+
106+
---
107+
name: sgpr32_to_spgr16
108+
body: |
109+
bb.0:
110+
; GCN-LABEL: name: sgpr32_to_spgr16
111+
; GCN: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
112+
; GCN-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:vgpr_32 = SUBREG_TO_REG 0, [[DEF]], %subreg.lo16
113+
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[SUBREG_TO_REG]]
114+
; GCN-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:vgpr_32 = SUBREG_TO_REG 0, [[COPY]], %subreg.lo16
115+
; GCN-NEXT: [[V_FMAC_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_FMAC_F16_t16_e64 0, [[SUBREG_TO_REG1]].lo16, 0, [[SUBREG_TO_REG1]].lo16, 0, [[SUBREG_TO_REG]].lo16, 0, 0, 0, implicit $mode, implicit $exec
116+
%0:vgpr_16 = IMPLICIT_DEF
117+
%1:sreg_32 = COPY %0:vgpr_16
118+
%2:sgpr_lo16 = COPY %1:sreg_32
119+
%3:sreg_32 = COPY %2:sgpr_lo16
120+
%4:sreg_32 = S_FMAC_F16 %3:sreg_32, %3:sreg_32, %1:sreg_32, implicit $mode
121+
...
122+
57123
---
58124
name: vgpr16_to_spgr32
59125
body: |

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