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Thorsten Schütt
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[GlobalISel][AArch64] Legalize G_SPLAT_VECTOR
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‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

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@@ -148,6 +148,7 @@ def : GINodeEquiv<G_INSERT_VECTOR_ELT, vector_insert>;
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def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>;
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def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
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def : GINodeEquiv<G_EXTRACT_SUBVECTOR, extract_subvector>;
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def : GINodeEquiv<G_SPLAT_VECTOR, splat_vector>;
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def : GINodeEquiv<G_FCEIL, fceil>;
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def : GINodeEquiv<G_FCOS, fcos>;
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def : GINodeEquiv<G_FSIN, fsin>;

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

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@@ -1316,6 +1316,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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.widenScalarOrEltToNextPow2(0)
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.immIdx(0); // Inform verifier imm idx 0 is handled.
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// TODO: {nxv8s16, s16}
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getActionDefinitionsBuilder(G_SPLAT_VECTOR)
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.legalFor(HasSVE, {{nxv4s32, s32}, {nxv2s64, s64}});
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getLegacyLegalizerInfo().computeTables();
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verify(*ST.getInstrInfo());
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}

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -debug -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=instruction-select %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SELECT
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# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=regbankselect %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-REGBANK
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# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LEGAL
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---
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name: test_splat_vector_s64
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body: |
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bb.1:
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; CHECK-SELECT-LABEL: name: test_splat_vector_s64
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; CHECK-SELECT: %imm:gpr64sp = COPY $x0
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; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D %imm
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; CHECK-SELECT-NEXT: $z0 = COPY %splat
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;
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; CHECK-REGBANK-LABEL: name: test_splat_vector_s64
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; CHECK-REGBANK: %imm:gpr(s64) = COPY $x0
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; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
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; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
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;
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; CHECK-LEGAL-LABEL: name: test_splat_vector_s64
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; CHECK-LEGAL: %imm:_(s64) = COPY $x0
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; CHECK-LEGAL-NEXT: %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
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; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
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%imm:_(s64) = COPY $x0
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%splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
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$z0 = COPY %splat(<vscale x 2 x s64>)
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...
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---
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name: test_splat_vector_s64_const
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body: |
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bb.1:
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; CHECK-SELECT-LABEL: name: test_splat_vector_s64_const
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; CHECK-SELECT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 9
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; CHECK-SELECT-NEXT: %imm:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D %imm
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; CHECK-SELECT-NEXT: $z0 = COPY %splat
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;
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; CHECK-REGBANK-LABEL: name: test_splat_vector_s64_const
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; CHECK-REGBANK: %imm:gpr(s64) = G_CONSTANT i64 9
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; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
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; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
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;
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; CHECK-LEGAL-LABEL: name: test_splat_vector_s64_const
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; CHECK-LEGAL: %imm:_(s64) = G_CONSTANT i64 9
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; CHECK-LEGAL-NEXT: %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
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; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
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%imm:_(s64) = G_CONSTANT i64 9
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%splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
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$z0 = COPY %splat(<vscale x 2 x s64>)
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...
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---
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name: test_splat_vector_s64_fconst
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body: |
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bb.1:
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; CHECK-SELECT-LABEL: name: test_splat_vector_s64_fconst
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; CHECK-SELECT: %imm:fpr64 = FMOVDi 34
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; CHECK-SELECT-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY %imm
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; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D [[COPY]]
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; CHECK-SELECT-NEXT: $z0 = COPY %splat
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;
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; CHECK-REGBANK-LABEL: name: test_splat_vector_s64_fconst
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; CHECK-REGBANK: %imm:fpr(s64) = G_FCONSTANT double 9.000000e+00
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; CHECK-REGBANK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY %imm(s64)
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; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[COPY]](s64)
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; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
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;
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; CHECK-LEGAL-LABEL: name: test_splat_vector_s64_fconst
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; CHECK-LEGAL: %imm:_(s64) = G_FCONSTANT double 9.000000e+00
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; CHECK-LEGAL-NEXT: %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
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; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
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%imm:_(s64) = G_FCONSTANT double 9.0
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%splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
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$z0 = COPY %splat(<vscale x 2 x s64>)
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...
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---
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name: test_splat_vector_s32
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body: |
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bb.1:
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; CHECK-SELECT-LABEL: name: test_splat_vector_s32
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; CHECK-SELECT: %imm:gpr32sp = COPY $w0
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; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S %imm
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; CHECK-SELECT-NEXT: $z0 = COPY %splat
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;
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; CHECK-REGBANK-LABEL: name: test_splat_vector_s32
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; CHECK-REGBANK: %imm:gpr(s32) = COPY $w0
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; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
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; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
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;
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; CHECK-LEGAL-LABEL: name: test_splat_vector_s32
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; CHECK-LEGAL: %imm:_(s32) = COPY $w0
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; CHECK-LEGAL-NEXT: %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
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; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
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%imm:_(s32) = COPY $w0
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%splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
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$z0 = COPY %splat(<vscale x 4 x s32>)
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...
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---
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name: test_splat_vector_s32_const
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body: |
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bb.1:
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; CHECK-SELECT-LABEL: name: test_splat_vector_s32_const
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; CHECK-SELECT: %imm:gpr32common = MOVi32imm 9
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; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S %imm
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; CHECK-SELECT-NEXT: $z0 = COPY %splat
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;
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; CHECK-REGBANK-LABEL: name: test_splat_vector_s32_const
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; CHECK-REGBANK: %imm:gpr(s32) = G_CONSTANT i32 9
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; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
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; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
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;
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; CHECK-LEGAL-LABEL: name: test_splat_vector_s32_const
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; CHECK-LEGAL: %imm:_(s32) = G_CONSTANT i32 9
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; CHECK-LEGAL-NEXT: %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
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; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
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%imm:_(s32) = G_CONSTANT i32 9
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%splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
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$z0 = COPY %splat(<vscale x 4 x s32>)
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...
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---
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name: test_splat_vector_s32_fconst
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body: |
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bb.1:
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; CHECK-SELECT-LABEL: name: test_splat_vector_s32_fconst
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; CHECK-SELECT: %imm:fpr32 = FMOVSi 28
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; CHECK-SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY %imm
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; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S [[COPY]]
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; CHECK-SELECT-NEXT: $z0 = COPY %splat
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;
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; CHECK-REGBANK-LABEL: name: test_splat_vector_s32_fconst
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; CHECK-REGBANK: %imm:fpr(s32) = G_FCONSTANT float 7.000000e+00
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; CHECK-REGBANK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %imm(s32)
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; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[COPY]](s32)
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; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
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;
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; CHECK-LEGAL-LABEL: name: test_splat_vector_s32_fconst
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; CHECK-LEGAL: %imm:_(s32) = G_FCONSTANT float 7.000000e+00
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; CHECK-LEGAL-NEXT: %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
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; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
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%imm:_(s32) = G_FCONSTANT float 7.0
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%splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
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$z0 = COPY %splat(<vscale x 4 x s32>)
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...

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