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[NewPM][AMDGPU] Add AMDGPUPassRegistry.def (#86095)
Move the pass registry to a separate file, prepare for porting dag-isel.
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‎llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def

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//===- AMDGPUPassRegistry.def - Registry of AMDGPU passes -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is used as the registry of passes that are part of the
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// AMDGPU backend.
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//
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//===----------------------------------------------------------------------===//
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// NOTE: NO INCLUDE GUARD DESIRED!
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#ifndef MODULE_PASS
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#define MODULE_PASS(NAME, CREATE_PASS)
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#endif
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MODULE_PASS("amdgpu-always-inline", AMDGPUAlwaysInlinePass())
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MODULE_PASS("amdgpu-attributor", AMDGPUAttributorPass(*this))
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MODULE_PASS("amdgpu-lower-buffer-fat-pointers",
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AMDGPULowerBufferFatPointersPass(*this))
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MODULE_PASS("amdgpu-lower-ctor-dtor", AMDGPUCtorDtorLoweringPass())
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MODULE_PASS("amdgpu-lower-module-lds", AMDGPULowerModuleLDSPass(*this))
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MODULE_PASS("amdgpu-printf-runtime-binding", AMDGPUPrintfRuntimeBindingPass())
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MODULE_PASS("amdgpu-unify-metadata", AMDGPUUnifyMetadataPass())
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#undef MODULE_PASS
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#ifndef FUNCTION_PASS
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#define FUNCTION_PASS(NAME, CREATE_PASS)
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#endif
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FUNCTION_PASS("amdgpu-codegenprepare", AMDGPUCodeGenPreparePass(*this))
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FUNCTION_PASS("amdgpu-image-intrinsic-opt",
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AMDGPUImageIntrinsicOptimizerPass(*this))
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FUNCTION_PASS("amdgpu-lower-kernel-arguments",
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AMDGPULowerKernelArgumentsPass(*this))
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FUNCTION_PASS("amdgpu-lower-kernel-attributes",
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AMDGPULowerKernelAttributesPass())
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FUNCTION_PASS("amdgpu-simplifylib", AMDGPUSimplifyLibCallsPass())
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FUNCTION_PASS("amdgpu-promote-alloca", AMDGPUPromoteAllocaPass(*this))
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FUNCTION_PASS("amdgpu-promote-alloca-to-vector",
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AMDGPUPromoteAllocaToVectorPass(*this))
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FUNCTION_PASS("amdgpu-promote-kernel-arguments",
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AMDGPUPromoteKernelArgumentsPass())
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FUNCTION_PASS("amdgpu-rewrite-undef-for-phi", AMDGPURewriteUndefForPHIPass())
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FUNCTION_PASS("amdgpu-unify-divergent-exit-nodes",
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AMDGPUUnifyDivergentExitNodesPass())
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FUNCTION_PASS("amdgpu-usenative", AMDGPUUseNativeCallsPass())
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#undef FUNCTION_PASS
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#ifndef FUNCTION_ANALYSIS
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#define FUNCTION_ANALYSIS(NAME, CREATE_PASS)
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#endif
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#ifndef FUNCTION_ALIAS_ANALYSIS
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#define FUNCTION_ALIAS_ANALYSIS(NAME, CREATE_PASS) \
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FUNCTION_ANALYSIS(NAME, CREATE_PASS)
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#endif
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FUNCTION_ALIAS_ANALYSIS("amdgpu-aa", AMDGPUAA())
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#undef FUNCTION_ALIAS_ANALYSIS
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#undef FUNCTION_ANALYSIS
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#ifndef FUNCTION_PASS_WITH_PARAMS
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#define FUNCTION_PASS_WITH_PARAMS(NAME, CLASS, CREATE_PASS, PARSER, PARAMS)
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#endif
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FUNCTION_PASS_WITH_PARAMS(
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"amdgpu-atomic-optimizer",
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"AMDGPUAtomicOptimizerPass",
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[=](ScanOptions Strategy) {
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return AMDGPUAtomicOptimizerPass(*this, Strategy);
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},
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parseAMDGPUAtomicOptimizerStrategy, "strategy=dpp|iterative|none")
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#undef FUNCTION_PASS_WITH_PARAMS

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 17 additions & 98 deletions
Original file line numberDiff line numberDiff line change
@@ -631,107 +631,26 @@ void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
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AAM.registerFunctionAnalysis<AMDGPUAA>();
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}
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static Expected<ScanOptions>
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parseAMDGPUAtomicOptimizerStrategy(StringRef Params) {
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if (Params.empty())
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return ScanOptions::Iterative;
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Params.consume_front("strategy=");
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auto Result = StringSwitch<std::optional<ScanOptions>>(Params)
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.Case("dpp", ScanOptions::DPP)
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.Cases("iterative", "", ScanOptions::Iterative)
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.Case("none", ScanOptions::None)
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.Default(std::nullopt);
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if (Result)
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return *Result;
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return make_error<StringError>("invalid parameter", inconvertibleErrorCode());
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}
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void AMDGPUTargetMachine::registerPassBuilderCallbacks(
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PassBuilder &PB, bool PopulateClassToPassNames) {
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PB.registerPipelineParsingCallback(
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[this](StringRef PassName, ModulePassManager &PM,
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ArrayRef<PassBuilder::PipelineElement>) {
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if (PassName == "amdgpu-attributor") {
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PM.addPass(AMDGPUAttributorPass(*this));
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return true;
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}
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if (PassName == "amdgpu-unify-metadata") {
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PM.addPass(AMDGPUUnifyMetadataPass());
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return true;
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}
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if (PassName == "amdgpu-printf-runtime-binding") {
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PM.addPass(AMDGPUPrintfRuntimeBindingPass());
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return true;
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}
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if (PassName == "amdgpu-always-inline") {
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PM.addPass(AMDGPUAlwaysInlinePass());
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return true;
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}
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if (PassName == "amdgpu-lower-module-lds") {
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PM.addPass(AMDGPULowerModuleLDSPass(*this));
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return true;
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}
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if (PassName == "amdgpu-lower-buffer-fat-pointers") {
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PM.addPass(AMDGPULowerBufferFatPointersPass(*this));
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return true;
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}
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if (PassName == "amdgpu-lower-ctor-dtor") {
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PM.addPass(AMDGPUCtorDtorLoweringPass());
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return true;
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}
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return false;
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});
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PB.registerPipelineParsingCallback(
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[this](StringRef PassName, FunctionPassManager &PM,
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ArrayRef<PassBuilder::PipelineElement>) {
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if (PassName == "amdgpu-simplifylib") {
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PM.addPass(AMDGPUSimplifyLibCallsPass());
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return true;
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}
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if (PassName == "amdgpu-image-intrinsic-opt") {
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PM.addPass(AMDGPUImageIntrinsicOptimizerPass(*this));
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return true;
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}
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if (PassName == "amdgpu-usenative") {
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PM.addPass(AMDGPUUseNativeCallsPass());
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return true;
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}
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if (PassName == "amdgpu-promote-alloca") {
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PM.addPass(AMDGPUPromoteAllocaPass(*this));
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return true;
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}
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if (PassName == "amdgpu-promote-alloca-to-vector") {
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PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
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return true;
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}
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if (PassName == "amdgpu-lower-kernel-attributes") {
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PM.addPass(AMDGPULowerKernelAttributesPass());
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return true;
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}
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if (PassName == "amdgpu-promote-kernel-arguments") {
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PM.addPass(AMDGPUPromoteKernelArgumentsPass());
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return true;
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}
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if (PassName == "amdgpu-unify-divergent-exit-nodes") {
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PM.addPass(AMDGPUUnifyDivergentExitNodesPass());
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return true;
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}
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if (PassName == "amdgpu-atomic-optimizer") {
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PM.addPass(
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AMDGPUAtomicOptimizerPass(*this, AMDGPUAtomicOptimizerStrategy));
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return true;
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}
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if (PassName == "amdgpu-codegenprepare") {
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PM.addPass(AMDGPUCodeGenPreparePass(*this));
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return true;
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}
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if (PassName == "amdgpu-lower-kernel-arguments") {
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PM.addPass(AMDGPULowerKernelArgumentsPass(*this));
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return true;
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}
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if (PassName == "amdgpu-rewrite-undef-for-phi") {
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PM.addPass(AMDGPURewriteUndefForPHIPass());
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return true;
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}
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return false;
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});
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PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
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FAM.registerPass([&] { return AMDGPUAA(); });
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});
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728-
PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
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if (AAName == "amdgpu-aa") {
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AAM.registerFunctionAnalysis<AMDGPUAA>();
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return true;
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}
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return false;
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});
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#define GET_PASS_REGISTRY "AMDGPUPassRegistry.def"
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#include "llvm/Passes/TargetPassRegistry.inc"
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PB.registerPipelineStartEPCallback(
737656
[](ModulePassManager &PM, OptimizationLevel Level) {

‎llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -amdgpu-atomic-optimizer-strategy=Iterative -passes='amdgpu-atomic-optimizer,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-ITERATIVE %s
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -amdgpu-atomic-optimizer-strategy=DPP -passes='amdgpu-atomic-optimizer,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-DPP %s
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -passes='amdgpu-atomic-optimizer<strategy=iterative>,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-ITERATIVE %s
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -passes='amdgpu-atomic-optimizer<strategy=dpp>,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-DPP %s
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; Tests various combinations of uniform/divergent address and uniform/divergent value inputs of various types for atomic operations.
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; Optimization remains same for Iterative and DPP strategies when value in uniform. These different scan/reduction

‎llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan_fp.ll

Lines changed: 2 additions & 2 deletions
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2-
; RUN: opt -S -mtriple=amdgcn-- -amdgpu-atomic-optimizer-strategy=Iterative -passes='amdgpu-atomic-optimizer,verify<domtree>' %s | FileCheck -check-prefix=IR-ITERATIVE %s
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; RUN: opt -S -mtriple=amdgcn-- -amdgpu-atomic-optimizer-strategy=DPP -passes='amdgpu-atomic-optimizer,verify<domtree>' %s | FileCheck -check-prefix=IR-DPP %s
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; RUN: opt -S -mtriple=amdgcn-- -passes='amdgpu-atomic-optimizer<strategy=iterative>,verify<domtree>' %s | FileCheck -check-prefix=IR-ITERATIVE %s
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; RUN: opt -S -mtriple=amdgcn-- -passes='amdgpu-atomic-optimizer<strategy=dpp>,verify<domtree>' %s | FileCheck -check-prefix=IR-DPP %s
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declare i32 @llvm.amdgcn.workitem.id.x()
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define amdgpu_kernel void @global_atomic_fadd_uni_value(ptr addrspace(1) %ptr) #0 {
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; IR-ITERATIVE-LABEL: @global_atomic_fadd_uni_value(

‎llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll

Lines changed: 2 additions & 2 deletions
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@@ -1,6 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2-
; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -amdgpu-atomic-optimizer-strategy=Iterative -passes='amdgpu-atomic-optimizer,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-ITERATIVE %s
3-
; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -amdgpu-atomic-optimizer-strategy=DPP -passes='amdgpu-atomic-optimizer,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-DPP %s
2+
; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -passes='amdgpu-atomic-optimizer<strategy=iterative>,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-ITERATIVE %s
3+
; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx906 -passes='amdgpu-atomic-optimizer<strategy=dpp>,verify<domtree>' %s | FileCheck --check-prefixes=IR,IR-DPP %s
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; Tests various combinations of uniform/divergent address and uniform/divergent value inputs of various types for atomic operations.
66
; Optimization remains same for Iterative and DPP strategies when value in uniform. These different scan/reduction

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