[ARM][FPEnv] Lowering of fpenv intrinsics

The change implements lowering of `get_fpenv`, `set_fpenv` and
`reset_fpenv`.

Differential Revision: https://reviews.llvm.org/D81843

Author: spavloff

llvm/include/llvm/Target/TargetSelectionDAG.td

@@ -617,6 +617,9 @@ def strict_uint_to_fp : SDNode<"ISD::STRICT_UINT_TO_FP",
 def strict_fsetcc  : SDNode<"ISD::STRICT_FSETCC",  SDTSetCC, [SDNPHasChain]>;
 def strict_fsetccs : SDNode<"ISD::STRICT_FSETCCS", SDTSetCC, [SDNPHasChain]>;
 
+def get_fpenv      : SDNode<"ISD::GET_FPENV", SDTGetFPStateOp, [SDNPHasChain]>;
+def set_fpenv      : SDNode<"ISD::SET_FPENV", SDTSetFPStateOp, [SDNPHasChain]>;
+def reset_fpenv    : SDNode<"ISD::RESET_FPENV", SDTNone, [SDNPHasChain]>;
 def get_fpmode     : SDNode<"ISD::GET_FPMODE", SDTGetFPStateOp, [SDNPHasChain]>;
 def set_fpmode     : SDNode<"ISD::SET_FPMODE", SDTSetFPStateOp, [SDNPHasChain]>;
 def reset_fpmode   : SDNode<"ISD::RESET_FPMODE", SDTNone, [SDNPHasChain]>;

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -1411,6 +1411,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::BITCAST, MVT::i64, Custom);
     setOperationAction(ISD::GET_ROUNDING, MVT::i32, Custom);
     setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
+    setOperationAction(ISD::GET_FPENV, MVT::i32, Legal);
+    setOperationAction(ISD::SET_FPENV, MVT::i32, Legal);
+    setOperationAction(ISD::RESET_FPENV, MVT::Other, Legal);
   }
 
   // We want to custom lower some of our intrinsics.

llvm/lib/Target/ARM/ARMInstrVFP.td

@@ -2670,6 +2670,12 @@ def : Pat<(f32 (vfp_f32f16imm:$imm)),
   let Predicates = [HasFullFP16];
 }
 
+// Floating-point environment management.
+def : Pat<(get_fpenv), (VMRS)>;
+def : Pat<(set_fpenv GPRnopc:$Rt), (VMSR GPRnopc:$Rt)>;
+def : Pat<(reset_fpenv), (VMSR (MOVi 0))>, Requires<[IsARM]>;
+def : Pat<(reset_fpenv), (VMSR (tMOVi8 0))>, Requires<[IsThumb]>;
+
 //===----------------------------------------------------------------------===//
 // Assembler aliases.
 //

llvm/test/CodeGen/ARM/fpenv.ll

@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+vfp2 %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+vfp2 --verify-machineinstrs %s -o - | FileCheck %s
 
 define void @func_02(i32 %rm) {
 ; CHECK-LABEL: func_02:
@@ -79,6 +79,16 @@ entry:
   ret i32 %fpenv
 }
 
+define i32 @get_fpenv_02() nounwind {
+; CHECK-LABEL: get_fpenv_02:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmrs r0, fpscr
+; CHECK-NEXT:    mov pc, lr
+entry:
+  %fpenv = call i32 @llvm.get.fpenv.i32()
+  ret i32 %fpenv
+}
+
 define void @set_fpenv_01(i32 %fpenv) #0 {
 ; CHECK-LABEL: set_fpenv_01:
 ; CHECK:       @ %bb.0: @ %entry
@@ -97,6 +107,16 @@ entry:
   ret void
 }
 
+define void @set_fpenv_02(i32 %fpenv) nounwind {
+; CHECK-LABEL: set_fpenv_02:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr fpscr, r0
+; CHECK-NEXT:    mov pc, lr
+entry:
+  call void @llvm.set.fpenv.i32(i32 %fpenv)
+  ret void
+}
+
 define void @reset_fpenv_01() #0 {
 ; CHECK-LABEL: reset_fpenv_01:
 ; CHECK:       @ %bb.0: @ %entry
@@ -111,6 +131,17 @@ entry:
   ret void
 }
 
+define void @reset_fpenv_02() nounwind {
+; CHECK-LABEL: reset_fpenv_02:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    mov r0, #0
+; CHECK-NEXT:    vmsr fpscr, r0
+; CHECK-NEXT:    mov pc, lr
+entry:
+  call void @llvm.reset.fpenv()
+  ret void
+}
+
 attributes #0 = { nounwind "use-soft-float"="true" }
 
 declare void @llvm.set.rounding(i32)