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[RISCV][NFC] Change type of isOrdered to boolean
The name is `isOrdered` but it's a string actually, which is a bit confusing. We change its type to `bit` and get the order string via its value. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D156306
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‎llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -207,23 +207,23 @@ class VSSSched<int eew, string emul, bit forceMasked = 0> : SchedCommon<
207207
class VSSSchedMC<int eew> : VSSSched<eew, "WorstCase", forceMasked=1>;
208208

209209
// Vector Indexed Loads and Stores
210-
class VLXSched<int dataEEW, string isOrdered, string dataEMUL, string idxEMUL,
210+
class VLXSched<int dataEEW, bit isOrdered, string dataEMUL, string idxEMUL,
211211
bit forceMasked = 0> : SchedCommon<
212-
[!cast<SchedWrite>("WriteVLD" # isOrdered # "X" # dataEEW # "_" # dataEMUL)],
213-
[ReadVLDX, !cast<SchedRead>("ReadVLD" # isOrdered # "XV_" # idxEMUL)],
212+
[!cast<SchedWrite>("WriteVLD" # !if(isOrdered, "O", "U") # "X" # dataEEW # "_" # dataEMUL)],
213+
[ReadVLDX, !cast<SchedRead>("ReadVLD" # !if(isOrdered, "O", "U") # "XV_" # idxEMUL)],
214214
dataEMUL, dataEEW, forceMasked
215215
>;
216-
class VLXSchedMC<int dataEEW, string isOrdered>:
216+
class VLXSchedMC<int dataEEW, bit isOrdered>:
217217
VLXSched<dataEEW, isOrdered, "WorstCase", "WorstCase", forceMasked=1>;
218218

219-
class VSXSched<int dataEEW, string isOrdered, string dataEMUL, string idxEMUL,
219+
class VSXSched<int dataEEW, bit isOrdered, string dataEMUL, string idxEMUL,
220220
bit forceMasked = 0> : SchedCommon<
221-
[!cast<SchedWrite>("WriteVST" # isOrdered # "X" # dataEEW # "_" # dataEMUL)],
222-
[!cast<SchedRead>("ReadVST" # isOrdered #"X" # dataEEW # "_" # dataEMUL),
223-
ReadVSTX, !cast<SchedRead>("ReadVST" # isOrdered # "XV_" # idxEMUL)],
221+
[!cast<SchedWrite>("WriteVST" # !if(isOrdered, "O", "U") # "X" # dataEEW # "_" # dataEMUL)],
222+
[!cast<SchedRead>("ReadVST" # !if(isOrdered, "O", "U") #"X" # dataEEW # "_" # dataEMUL),
223+
ReadVSTX, !cast<SchedRead>("ReadVST" # !if(isOrdered, "O", "U") # "XV_" # idxEMUL)],
224224
dataEMUL, dataEEW, forceMasked
225225
>;
226-
class VSXSchedMC<int dataEEW, string isOrdered>:
226+
class VSXSchedMC<int dataEEW, bit isOrdered>:
227227
VSXSched<dataEEW, isOrdered, "WorstCase", "WorstCase", forceMasked=1>;
228228

229229
// Unit-stride Fault-Only-First Loads
@@ -272,24 +272,24 @@ class VSSSEGSchedMC<int nf, int eew> : VSSSEGSched<nf, eew, "WorstCase",
272272
forceMasked=1>;
273273

274274
// Indexed Segment Loads and Stores
275-
class VLXSEGSched<int nf, int eew, string isOrdered, string emul,
275+
class VLXSEGSched<int nf, int eew, bit isOrdered, string emul,
276276
bit forceMasked = 0> : SchedCommon<
277-
[!cast<SchedWrite>("WriteVL" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul)],
278-
[ReadVLDX, !cast<SchedRead>("ReadVLD" #isOrdered #"XV_" #emul)],
277+
[!cast<SchedWrite>("WriteVL" #!if(isOrdered, "O", "U") #"XSEG" #nf #"e" #eew #"_" #emul)],
278+
[ReadVLDX, !cast<SchedRead>("ReadVLD" #!if(isOrdered, "O", "U") #"XV_" #emul)],
279279
emul, eew, forceMasked
280280
>;
281-
class VLXSEGSchedMC<int nf, int eew, string isOrdered>:
281+
class VLXSEGSchedMC<int nf, int eew, bit isOrdered>:
282282
VLXSEGSched<nf, eew, isOrdered, "WorstCase", forceMasked=1>;
283283

284284
// Passes sew=0 instead of eew=0 since this pseudo does not follow MX_E form.
285-
class VSXSEGSched<int nf, int eew, string isOrdered, string emul,
285+
class VSXSEGSched<int nf, int eew, bit isOrdered, string emul,
286286
bit forceMasked = 0> : SchedCommon<
287-
[!cast<SchedWrite>("WriteVS" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul)],
288-
[!cast<SchedRead>("ReadVST" #isOrdered #"X" #eew #"_" #emul),
289-
ReadVSTX, !cast<SchedRead>("ReadVST" #isOrdered #"XV_" #emul)],
287+
[!cast<SchedWrite>("WriteVS" #!if(isOrdered, "O", "U") #"XSEG" #nf #"e" #eew #"_" #emul)],
288+
[!cast<SchedRead>("ReadVST" #!if(isOrdered, "O", "U") #"X" #eew #"_" #emul),
289+
ReadVSTX, !cast<SchedRead>("ReadVST" #!if(isOrdered, "O", "U") #"XV_" #emul)],
290290
emul, sew=0, forceMasked=forceMasked
291291
>;
292-
class VSXSEGSchedMC<int nf, int eew, string isOrdered>:
292+
class VSXSEGSchedMC<int nf, int eew, bit isOrdered>:
293293
VSXSEGSched<nf, eew, isOrdered, "WorstCase", forceMasked=1>;
294294

295295
//===----------------------------------------------------------------------===//
@@ -539,17 +539,17 @@ multiclass VIndexLoadStore<list<int> EEWList> {
539539

540540
def VLUXEI # n # _V :
541541
VIndexedLoad<MOPLDIndexedUnord, w, "vluxei" # n # ".v">,
542-
VLXSchedMC<n, "U">;
542+
VLXSchedMC<n, isOrdered=0>;
543543
def VLOXEI # n # _V :
544544
VIndexedLoad<MOPLDIndexedOrder, w, "vloxei" # n # ".v">,
545-
VLXSchedMC<n, "O">;
545+
VLXSchedMC<n, isOrdered=1>;
546546

547547
def VSUXEI # n # _V :
548548
VIndexedStore<MOPSTIndexedUnord, w, "vsuxei" # n # ".v">,
549-
VSXSchedMC<n, "U">;
549+
VSXSchedMC<n, isOrdered=0>;
550550
def VSOXEI # n # _V :
551551
VIndexedStore<MOPSTIndexedOrder, w, "vsoxei" # n # ".v">,
552-
VSXSchedMC<n, "O">;
552+
VSXSchedMC<n, isOrdered=1>;
553553
}
554554
}
555555

@@ -1742,19 +1742,19 @@ let Predicates = [HasVInstructions] in {
17421742
def VLUXSEG#nf#EI#eew#_V :
17431743
VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, w,
17441744
"vluxseg"#nf#"ei"#eew#".v">,
1745-
VLXSEGSchedMC<nf, eew, "U">;
1745+
VLXSEGSchedMC<nf, eew, isOrdered=0>;
17461746
def VLOXSEG#nf#EI#eew#_V :
17471747
VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, w,
17481748
"vloxseg"#nf#"ei"#eew#".v">,
1749-
VLXSEGSchedMC<nf, eew, "O">;
1749+
VLXSEGSchedMC<nf, eew, isOrdered=1>;
17501750
def VSUXSEG#nf#EI#eew#_V :
17511751
VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, w,
17521752
"vsuxseg"#nf#"ei"#eew#".v">,
1753-
VSXSEGSchedMC<nf, eew, "U">;
1753+
VSXSEGSchedMC<nf, eew, isOrdered=0>;
17541754
def VSOXSEG#nf#EI#eew#_V :
17551755
VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, w,
17561756
"vsoxseg"#nf#"ei"#eew#".v">,
1757-
VSXSEGSchedMC<nf, eew, "O">;
1757+
VSXSEGSchedMC<nf, eew, isOrdered=1>;
17581758
}
17591759
}
17601760
} // Predicates = [HasVInstructions]
@@ -1787,19 +1787,19 @@ let Predicates = [HasVInstructionsI64, IsRV64] in {
17871787
def VLUXSEG #nf #EI64_V
17881788
: VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, LSWidth64,
17891789
"vluxseg" #nf #"ei64.v">,
1790-
VLXSEGSchedMC<nf, 64, "U">;
1790+
VLXSEGSchedMC<nf, 64, isOrdered=0>;
17911791
def VLOXSEG #nf #EI64_V
17921792
: VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, LSWidth64,
17931793
"vloxseg" #nf #"ei64.v">,
1794-
VLXSEGSchedMC<nf, 64, "O">;
1794+
VLXSEGSchedMC<nf, 64, isOrdered=1>;
17951795
def VSUXSEG #nf #EI64_V
17961796
: VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, LSWidth64,
17971797
"vsuxseg" #nf #"ei64.v">,
1798-
VSXSEGSchedMC<nf, 64, "U">;
1798+
VSXSEGSchedMC<nf, 64, isOrdered=0>;
17991799
def VSOXSEG #nf #EI64_V
18001800
: VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth64,
18011801
"vsoxseg" #nf #"ei64.v">,
1802-
VSXSEGSchedMC<nf, 64, "O">;
1802+
VSXSEGSchedMC<nf, 64, isOrdered=1>;
18031803
}
18041804
} // Predicates = [HasVInstructionsI64, IsRV64]
18051805

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1782,15 +1782,14 @@ multiclass VPseudoILoad<bit Ordered> {
17821782
defvar Vreg = dataEMUL.vrclass;
17831783
defvar IdxVreg = idxEMUL.vrclass;
17841784
defvar HasConstraint = !ne(dataEEW, idxEEW);
1785-
defvar Order = !if(Ordered, "O", "U");
17861785
let VLMul = dataEMUL.value in {
17871786
def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
17881787
VPseudoILoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
1789-
VLXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
1788+
VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
17901789
def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
17911790
VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
17921791
RISCVMaskedPseudo<MaskIdx=3>,
1793-
VLXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
1792+
VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
17941793
}
17951794
}
17961795
}
@@ -1853,14 +1852,13 @@ multiclass VPseudoIStore<bit Ordered> {
18531852
defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
18541853
defvar Vreg = dataEMUL.vrclass;
18551854
defvar IdxVreg = idxEMUL.vrclass;
1856-
defvar Order = !if(Ordered, "O", "U");
18571855
let VLMul = dataEMUL.value in {
18581856
def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
18591857
VPseudoIStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
1860-
VSXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
1858+
VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
18611859
def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
18621860
VPseudoIStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
1863-
VSXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
1861+
VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
18641862
}
18651863
}
18661864
}
@@ -3539,18 +3537,17 @@ multiclass VPseudoISegLoad<bit Ordered> {
35393537
defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
35403538
defvar DataVreg = dataEMUL.vrclass;
35413539
defvar IdxVreg = idxEMUL.vrclass;
3542-
defvar Order = !if(Ordered, "O", "U");
35433540
let VLMul = dataEMUL.value in {
35443541
foreach nf = NFSet<dataEMUL>.L in {
35453542
defvar Vreg = SegRegClass<dataEMUL, nf>.RC;
35463543
def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
35473544
VPseudoISegLoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
35483545
nf, Ordered>,
3549-
VLXSEGSched<nf, dataEEW, Order, DataLInfo>;
3546+
VLXSEGSched<nf, dataEEW, Ordered, DataLInfo>;
35503547
def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
35513548
VPseudoISegLoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
35523549
nf, Ordered>,
3553-
VLXSEGSched<nf, dataEEW, Order, DataLInfo>;
3550+
VLXSEGSched<nf, dataEEW, Ordered, DataLInfo>;
35543551
}
35553552
}
35563553
}
@@ -3606,18 +3603,17 @@ multiclass VPseudoISegStore<bit Ordered> {
36063603
defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
36073604
defvar DataVreg = dataEMUL.vrclass;
36083605
defvar IdxVreg = idxEMUL.vrclass;
3609-
defvar Order = !if(Ordered, "O", "U");
36103606
let VLMul = dataEMUL.value in {
36113607
foreach nf = NFSet<dataEMUL>.L in {
36123608
defvar Vreg = SegRegClass<dataEMUL, nf>.RC;
36133609
def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
36143610
VPseudoISegStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
36153611
nf, Ordered>,
3616-
VSXSEGSched<nf, idxEEW, Order, DataLInfo>;
3612+
VSXSEGSched<nf, idxEEW, Ordered, DataLInfo>;
36173613
def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
36183614
VPseudoISegStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
36193615
nf, Ordered>,
3620-
VSXSEGSched<nf, idxEEW, Order, DataLInfo>;
3616+
VSXSEGSched<nf, idxEEW, Ordered, DataLInfo>;
36213617
}
36223618
}
36233619
}

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