Skip to content

Commit a361a3d

Browse files
yashnatoryashnator
authored
[llvm][InstCombine] Fold select to cmp for weak and inverted inequalities (#143445)
1 parent 6f999a5 commit a361a3d

File tree

2 files changed

+315
-0
lines changed

2 files changed

+315
-0
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3631,6 +3631,28 @@ Instruction *InstCombinerImpl::foldSelectToCmp(SelectInst &SI) {
36313631
if (!LHS->getType()->isIntOrIntVectorTy())
36323632
return nullptr;
36333633

3634+
// If there is no -1, 0 or 1 at TV, then invert the select statement and try
3635+
// to canonicalize to one of the forms above
3636+
if (!isa<Constant>(TV)) {
3637+
if (!isa<Constant>(FV))
3638+
return nullptr;
3639+
Pred = ICmpInst::getInverseCmpPredicate(Pred);
3640+
std::swap(TV, FV);
3641+
}
3642+
3643+
if (ICmpInst::isNonStrictPredicate(Pred)) {
3644+
if (Constant *C = dyn_cast<Constant>(RHS)) {
3645+
auto FlippedPredAndConst =
3646+
getFlippedStrictnessPredicateAndConstant(Pred, C);
3647+
if (!FlippedPredAndConst)
3648+
return nullptr;
3649+
Pred = FlippedPredAndConst->first;
3650+
RHS = FlippedPredAndConst->second;
3651+
} else {
3652+
return nullptr;
3653+
}
3654+
}
3655+
36343656
// Try to swap operands and the predicate. We need to be careful when doing
36353657
// so because two of the patterns have opposite predicates, so use the
36363658
// constant inside select to determine if swapping operands would be

‎llvm/test/Transforms/InstCombine/select-to-cmp.ll

Lines changed: 293 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,293 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -passes=instcombine -S < %s | FileCheck %s
3+
4+
; Tests for select to scmp
5+
6+
define i32 @scmp_x_0_inverted(i32 %x) {
7+
; CHECK-LABEL: define i32 @scmp_x_0_inverted(
8+
; CHECK-SAME: i32 [[X:%.*]]) {
9+
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[X]], i32 0)
10+
; CHECK-NEXT: ret i32 [[TMP1]]
11+
;
12+
%2 = icmp ne i32 %x, 0
13+
%3 = zext i1 %2 to i32
14+
%4 = icmp sgt i32 %x, -1
15+
%5 = select i1 %4, i32 %3, i32 -1
16+
ret i32 %5
17+
}
18+
19+
; y = -10
20+
define i32 @scmp_x_0_inverted_const_neg10(i32 %x) {
21+
; CHECK-LABEL: define i32 @scmp_x_0_inverted_const_neg10(
22+
; CHECK-SAME: i32 [[X:%.*]]) {
23+
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[X]], i32 -10)
24+
; CHECK-NEXT: ret i32 [[TMP1]]
25+
;
26+
%1 = icmp ne i32 %x, -10
27+
%2 = zext i1 %1 to i32
28+
%3 = icmp sgt i32 %x, -11
29+
%4 = select i1 %3, i32 %2, i32 -1
30+
ret i32 %4
31+
}
32+
33+
; y = 7 (i8)
34+
define i8 @scmp_x_0_inverted_i8(i8 %x) {
35+
; CHECK-LABEL: define i8 @scmp_x_0_inverted_i8(
36+
; CHECK-SAME: i8 [[X:%.*]]) {
37+
; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.scmp.i8.i8(i8 [[X]], i8 7)
38+
; CHECK-NEXT: ret i8 [[TMP1]]
39+
;
40+
%1 = icmp ne i8 %x, 7
41+
%2 = zext i1 %1 to i8
42+
%3 = icmp sgt i8 %x, 6
43+
%4 = select i1 %3, i8 %2, i8 -1
44+
ret i8 %4
45+
}
46+
47+
; scmp using ints of two kinds- i32 and i64
48+
define i32 @scmp_x_0_inverted_i64_neq(i32 %x) {
49+
; CHECK-LABEL: define i32 @scmp_x_0_inverted_i64_neq(
50+
; CHECK-SAME: i32 [[X:%.*]]) {
51+
; CHECK-NEXT: [[SEL:%.*]] = call i64 @llvm.scmp.i64.i32(i32 [[X]], i32 0)
52+
; CHECK-NEXT: [[RET:%.*]] = trunc i64 [[SEL]] to i32
53+
; CHECK-NEXT: ret i32 [[RET]]
54+
;
55+
%x64 = sext i32 %x to i64
56+
%cmp1 = icmp ne i64 %x64, 0
57+
%zext = zext i1 %cmp1 to i64
58+
%cmp2 = icmp sgt i64 %x64, -1
59+
%sel = select i1 %cmp2, i64 %zext, i64 -1
60+
%ret = trunc i64 %sel to i32
61+
ret i32 %ret
62+
}
63+
64+
; Same example as previous but with inequality
65+
define i32 @scmp_x_0_inverted_i64_sgt(i32 %x) {
66+
; CHECK-LABEL: define i32 @scmp_x_0_inverted_i64_sgt(
67+
; CHECK-SAME: i32 [[X:%.*]]) {
68+
; CHECK-NEXT: [[SEL:%.*]] = call i64 @llvm.scmp.i64.i32(i32 [[X]], i32 0)
69+
; CHECK-NEXT: [[RET:%.*]] = trunc i64 [[SEL]] to i32
70+
; CHECK-NEXT: ret i32 [[RET]]
71+
;
72+
%x64 = sext i32 %x to i64
73+
%cmp1 = icmp sgt i64 %x64, 0
74+
%zext = zext i1 %cmp1 to i64
75+
%cmp2 = icmp sgt i64 %x64, -1
76+
%sel = select i1 %cmp2, i64 %zext, i64 -1
77+
%ret = trunc i64 %sel to i32
78+
ret i32 %ret
79+
}
80+
81+
; y = -1000
82+
define i32 @scmp_x_0_inverted_const_neg1000(i32 %x) {
83+
; CHECK-LABEL: define i32 @scmp_x_0_inverted_const_neg1000(
84+
; CHECK-SAME: i32 [[X:%.*]]) {
85+
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[X]], i32 -1000)
86+
; CHECK-NEXT: ret i32 [[TMP1]]
87+
;
88+
%1 = icmp sgt i32 %x, -1000
89+
%2 = zext i1 %1 to i32
90+
%3 = icmp sgt i32 %x, -1001
91+
%4 = select i1 %3, i32 %2, i32 -1
92+
ret i32 %4
93+
}
94+
95+
; y = 1729
96+
define i32 @scmp_x_0_inverted_const_1729_sgt(i32 %x) {
97+
; CHECK-LABEL: define i32 @scmp_x_0_inverted_const_1729_sgt(
98+
; CHECK-SAME: i32 [[X:%.*]]) {
99+
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[X]], i32 1729)
100+
; CHECK-NEXT: ret i32 [[TMP1]]
101+
;
102+
%1 = icmp sgt i32 %x, 1729
103+
%2 = zext i1 %1 to i32
104+
%3 = icmp sgt i32 %x, 1728
105+
%4 = select i1 %3, i32 %2, i32 -1
106+
ret i32 %4
107+
}
108+
109+
; ucmp with 10
110+
define i32 @ucmp_x_10_inverted(i32 %x) {
111+
; CHECK-LABEL: define i32 @ucmp_x_10_inverted(
112+
; CHECK-SAME: i32 [[X:%.*]]) {
113+
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ucmp.i32.i32(i32 [[X]], i32 10)
114+
; CHECK-NEXT: ret i32 [[TMP1]]
115+
;
116+
%1 = icmp ne i32 %x, 10
117+
%2 = zext i1 %1 to i32
118+
%3 = icmp ugt i32 %x, 9
119+
%4 = select i1 %3, i32 %2, i32 -1
120+
ret i32 %4
121+
}
122+
123+
; ucmp with -3, wraps around
124+
define i32 @ucmp_x_neg1_inverted(i32 %x) {
125+
; CHECK-LABEL: define i32 @ucmp_x_neg1_inverted(
126+
; CHECK-SAME: i32 [[X:%.*]]) {
127+
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ucmp.i32.i32(i32 [[X]], i32 -3)
128+
; CHECK-NEXT: ret i32 [[TMP1]]
129+
;
130+
%1 = icmp ne i32 %x, -3
131+
%2 = zext i1 %1 to i32
132+
%3 = icmp ugt i32 %x, -4
133+
%4 = select i1 %3, i32 %2, i32 -1
134+
ret i32 %4
135+
}
136+
137+
; ucmp with -4, wraps around
138+
define i8 @ucmp_x_neg4_i8_ugt(i8 %x) {
139+
; CHECK-LABEL: define i8 @ucmp_x_neg4_i8_ugt(
140+
; CHECK-SAME: i8 [[X:%.*]]) {
141+
; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ucmp.i8.i8(i8 [[X]], i8 -4)
142+
; CHECK-NEXT: ret i8 [[TMP1]]
143+
;
144+
%1 = icmp ugt i8 %x, -4
145+
%2 = zext i1 %1 to i8
146+
%3 = icmp ugt i8 %x, -5
147+
%4 = select i1 %3, i8 %2, i8 -1
148+
ret i8 %4
149+
}
150+
151+
; Vector tests
152+
153+
; Test with splat vec
154+
define <4 x i32> @scmp_x_0_inverted_splat_vec(<4 x i32> %x) {
155+
; CHECK-LABEL: define <4 x i32> @scmp_x_0_inverted_splat_vec(
156+
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
157+
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.scmp.v4i32.v4i32(<4 x i32> [[X]], <4 x i32> zeroinitializer)
158+
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
159+
;
160+
%2 = icmp ne <4 x i32> %x, zeroinitializer
161+
%3 = zext <4 x i1> %2 to <4 x i32>
162+
%4 = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
163+
%5 = select <4 x i1> %4, <4 x i32> %3, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
164+
ret <4 x i32> %5
165+
}
166+
167+
; Test with non-splat vector and different bitwidth
168+
define <4 x i32> @non_splat_vec_scmp_diff_bitwidth(<4 x i32> %x) {
169+
; CHECK-LABEL: define <4 x i32> @non_splat_vec_scmp_diff_bitwidth(
170+
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
171+
; CHECK-NEXT: [[SEL:%.*]] = call <4 x i64> @llvm.scmp.v4i64.v4i32(<4 x i32> [[X]], <4 x i32> <i32 0, i32 1, i32 -1, i32 5>)
172+
; CHECK-NEXT: [[RET:%.*]] = trunc <4 x i64> [[SEL]] to <4 x i32>
173+
; CHECK-NEXT: ret <4 x i32> [[RET]]
174+
;
175+
%x64 = sext <4 x i32> %x to <4 x i64>
176+
%cmp1 = icmp slt <4 x i64> %x64, <i64 0, i64 1, i64 -1, i64 5>
177+
%sext = sext <4 x i1> %cmp1 to <4 x i64>
178+
%cmp2 = icmp slt <4 x i64> %x64, <i64 1, i64 2, i64 0, i64 6>
179+
%sel = select <4 x i1> %cmp2, <4 x i64> %sext, <4 x i64> <i64 1, i64 1, i64 1, i64 1>
180+
%ret = trunc <4 x i64> %sel to <4 x i32>
181+
ret <4 x i32> %ret
182+
}
183+
184+
; Negative examples
185+
186+
; Not scmp due to wrong RHS of the predicate
187+
define i32 @scmp_ne_0(i32 %0) {
188+
; CHECK-LABEL: define i32 @scmp_ne_0(
189+
; CHECK-SAME: i32 [[TMP0:%.*]]) {
190+
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP0]], 0
191+
; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
192+
; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP0]], 1
193+
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i32 [[TMP3]], i32 -1
194+
; CHECK-NEXT: ret i32 [[TMP5]]
195+
;
196+
%2 = icmp ne i32 %0, 0
197+
%3 = zext i1 %2 to i32
198+
%4 = icmp sgt i32 %0, 1
199+
%5 = select i1 %4, i32 %3, i32 -1
200+
ret i32 %5
201+
}
202+
203+
; y = 0 with unsigned compare but RHS wraps
204+
define i32 @ucmp_x_0_inverted(i32 %x) {
205+
; CHECK-LABEL: define i32 @ucmp_x_0_inverted(
206+
; CHECK-SAME: i32 [[X:%.*]]) {
207+
; CHECK-NEXT: ret i32 -1
208+
;
209+
%1 = icmp ne i32 %x, 0
210+
%2 = zext i1 %1 to i32
211+
%3 = icmp ugt i32 %x, -1
212+
%4 = select i1 %3, i32 %2, i32 -1
213+
ret i32 %4
214+
}
215+
216+
; Don't fold with INT32_MIN
217+
define i32 @scmp_x_0_inverted_const_min(i32 %x) {
218+
; CHECK-LABEL: define i32 @scmp_x_0_inverted_const_min(
219+
; CHECK-SAME: i32 [[X:%.*]]) {
220+
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X]], -2147483648
221+
; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
222+
; CHECK-NEXT: ret i32 [[TMP2]]
223+
;
224+
%1 = icmp ne i32 %x, -2147483648
225+
%2 = zext i1 %1 to i32
226+
%3 = icmp sge i32 %x, -2147483648
227+
%4 = select i1 %3, i32 %2, i32 -1
228+
ret i32 %4
229+
}
230+
231+
; Unsigned cmp of zext of i32 with i64 -1 should always be -1
232+
define i32 @ucmp_x_0_inverted_i64_ugt(i32 %x) {
233+
; CHECK-LABEL: define i32 @ucmp_x_0_inverted_i64_ugt(
234+
; CHECK-SAME: i32 [[X:%.*]]) {
235+
; CHECK-NEXT: ret i32 -1
236+
;
237+
%x64 = zext i32 %x to i64
238+
%cmp1 = icmp ugt i64 %x64, 0
239+
%zext = zext i1 %cmp1 to i64
240+
%cmp2 = icmp ugt i64 %x64, -1
241+
%sel = select i1 %cmp2, i64 %zext, i64 -1
242+
%ret = trunc i64 %sel to i32
243+
ret i32 %ret
244+
}
245+
246+
; y = 4294967295 (UINT32_MAX), simply sign extend neq
247+
define i32 @ucmp_x_const_u32max(i32 %x) {
248+
; CHECK-LABEL: define i32 @ucmp_x_const_u32max(
249+
; CHECK-SAME: i32 [[X:%.*]]) {
250+
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X]], -1
251+
; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[TMP1]] to i32
252+
; CHECK-NEXT: ret i32 [[TMP2]]
253+
;
254+
%1 = icmp ugt i32 %x, 4294967295
255+
%2 = zext i1 %1 to i32
256+
%3 = icmp ugt i32 %x, 4294967294
257+
%4 = select i1 %3, i32 %2, i32 -1
258+
ret i32 %4
259+
}
260+
261+
; Don't fold with different signedness
262+
define i32 @different_signedness_neg(i32 %x) {
263+
; CHECK-LABEL: define i32 @different_signedness_neg(
264+
; CHECK-SAME: i32 [[X:%.*]]) {
265+
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[X]], -10
266+
; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
267+
; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[X]], -11
268+
; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 -1
269+
; CHECK-NEXT: ret i32 [[TMP4]]
270+
;
271+
%1 = icmp ugt i32 %x, -10
272+
%2 = zext i1 %1 to i32
273+
%3 = icmp sgt i32 %x, -11
274+
%4 = select i1 %3, i32 %2, i32 -1
275+
ret i32 %4
276+
}
277+
278+
; Test with wrong false value
279+
define <4 x i32> @scmp_x_0_inverted_vec(<4 x i32> %x) {
280+
; CHECK-LABEL: define <4 x i32> @scmp_x_0_inverted_vec(
281+
; CHECK-SAME: <4 x i32> [[X:%.*]]) {
282+
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <4 x i32> [[X]], zeroinitializer
283+
; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
284+
; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[X]], splat (i32 -1)
285+
; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[TMP2]], <4 x i32> <i32 -1, i32 -2, i32 -1, i32 -1>
286+
; CHECK-NEXT: ret <4 x i32> [[TMP4]]
287+
;
288+
%2 = icmp ne <4 x i32> %x, zeroinitializer
289+
%3 = zext <4 x i1> %2 to <4 x i32>
290+
%4 = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
291+
%5 = select <4 x i1> %4, <4 x i32> %3, <4 x i32> <i32 -1, i32 -2, i32 -1, i32 -1>
292+
ret <4 x i32> %5
293+
}

0 commit comments

Comments
 (0)