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HsiangkaiHsiangkai
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[RISCV] Spilling for RISC-V V extension. (2nd version)
Differential Revision: https://reviews.llvm.org/D95148
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7 files changed

+648
-19
lines changed

7 files changed

+648
-19
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 72 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -13,10 +13,12 @@
1313
#include "RISCVInstrInfo.h"
1414
#include "MCTargetDesc/RISCVMatInt.h"
1515
#include "RISCV.h"
16+
#include "RISCVMachineFunctionInfo.h"
1617
#include "RISCVSubtarget.h"
1718
#include "RISCVTargetMachine.h"
1819
#include "llvm/ADT/STLExtras.h"
1920
#include "llvm/ADT/SmallVector.h"
21+
#include "llvm/Analysis/MemoryLocation.h"
2022
#include "llvm/CodeGen/MachineFunctionPass.h"
2123
#include "llvm/CodeGen/MachineInstrBuilder.h"
2224
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -152,12 +154,10 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
152154
DL = I->getDebugLoc();
153155

154156
MachineFunction *MF = MBB.getParent();
155-
const MachineFrameInfo &MFI = MF->getFrameInfo();
156-
MachineMemOperand *MMO = MF->getMachineMemOperand(
157-
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
158-
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
157+
MachineFrameInfo &MFI = MF->getFrameInfo();
159158

160159
unsigned Opcode;
160+
bool IsScalableVector = false;
161161
if (RISCV::GPRRegClass.hasSubClassEq(RC))
162162
Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
163163
RISCV::SW : RISCV::SD;
@@ -167,14 +167,42 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
167167
Opcode = RISCV::FSW;
168168
else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
169169
Opcode = RISCV::FSD;
170-
else
170+
else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
171+
Opcode = RISCV::PseudoVSPILL_M1;
172+
IsScalableVector = true;
173+
} else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
174+
Opcode = RISCV::PseudoVSPILL_M2;
175+
IsScalableVector = true;
176+
} else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) {
177+
Opcode = RISCV::PseudoVSPILL_M4;
178+
IsScalableVector = true;
179+
} else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) {
180+
Opcode = RISCV::PseudoVSPILL_M8;
181+
IsScalableVector = true;
182+
} else
171183
llvm_unreachable("Can't store this register to stack slot");
172184

173-
BuildMI(MBB, I, DL, get(Opcode))
174-
.addReg(SrcReg, getKillRegState(IsKill))
175-
.addFrameIndex(FI)
176-
.addImm(0)
177-
.addMemOperand(MMO);
185+
if (IsScalableVector) {
186+
MachineMemOperand *MMO = MF->getMachineMemOperand(
187+
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
188+
MemoryLocation::UnknownSize, MFI.getObjectAlign(FI));
189+
190+
MFI.setStackID(FI, TargetStackID::ScalableVector);
191+
BuildMI(MBB, I, DL, get(Opcode))
192+
.addReg(SrcReg, getKillRegState(IsKill))
193+
.addFrameIndex(FI)
194+
.addMemOperand(MMO);
195+
} else {
196+
MachineMemOperand *MMO = MF->getMachineMemOperand(
197+
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
198+
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
199+
200+
BuildMI(MBB, I, DL, get(Opcode))
201+
.addReg(SrcReg, getKillRegState(IsKill))
202+
.addFrameIndex(FI)
203+
.addImm(0)
204+
.addMemOperand(MMO);
205+
}
178206
}
179207

180208
void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@@ -187,12 +215,10 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
187215
DL = I->getDebugLoc();
188216

189217
MachineFunction *MF = MBB.getParent();
190-
const MachineFrameInfo &MFI = MF->getFrameInfo();
191-
MachineMemOperand *MMO = MF->getMachineMemOperand(
192-
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
193-
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
218+
MachineFrameInfo &MFI = MF->getFrameInfo();
194219

195220
unsigned Opcode;
221+
bool IsScalableVector = false;
196222
if (RISCV::GPRRegClass.hasSubClassEq(RC))
197223
Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
198224
RISCV::LW : RISCV::LD;
@@ -202,13 +228,40 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
202228
Opcode = RISCV::FLW;
203229
else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
204230
Opcode = RISCV::FLD;
205-
else
231+
else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
232+
Opcode = RISCV::PseudoVRELOAD_M1;
233+
IsScalableVector = true;
234+
} else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
235+
Opcode = RISCV::PseudoVRELOAD_M2;
236+
IsScalableVector = true;
237+
} else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) {
238+
Opcode = RISCV::PseudoVRELOAD_M4;
239+
IsScalableVector = true;
240+
} else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) {
241+
Opcode = RISCV::PseudoVRELOAD_M8;
242+
IsScalableVector = true;
243+
} else
206244
llvm_unreachable("Can't load this register from stack slot");
207245

208-
BuildMI(MBB, I, DL, get(Opcode), DstReg)
209-
.addFrameIndex(FI)
210-
.addImm(0)
211-
.addMemOperand(MMO);
246+
if (IsScalableVector) {
247+
MachineMemOperand *MMO = MF->getMachineMemOperand(
248+
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
249+
MemoryLocation::UnknownSize, MFI.getObjectAlign(FI));
250+
251+
MFI.setStackID(FI, TargetStackID::ScalableVector);
252+
BuildMI(MBB, I, DL, get(Opcode), DstReg)
253+
.addFrameIndex(FI)
254+
.addMemOperand(MMO);
255+
} else {
256+
MachineMemOperand *MMO = MF->getMachineMemOperand(
257+
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
258+
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
259+
260+
BuildMI(MBB, I, DL, get(Opcode), DstReg)
261+
.addFrameIndex(FI)
262+
.addImm(0)
263+
.addMemOperand(MMO);
264+
}
212265
}
213266

214267
void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3155,6 +3155,20 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1,
31553155
Uses = [VL] in
31563156
def PseudoReadVL : Pseudo<(outs GPR:$rd), (ins), []>;
31573157

3158+
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1 in {
3159+
def PseudoVSPILL_M1 : VPseudo<VS1R_V, V_M1, (outs), (ins VR:$rs1, GPR:$rs2)>;
3160+
def PseudoVSPILL_M2 : VPseudo<VS2R_V, V_M2, (outs), (ins VRM2:$rs1, GPR:$rs2)>;
3161+
def PseudoVSPILL_M4 : VPseudo<VS4R_V, V_M4, (outs), (ins VRM4:$rs1, GPR:$rs2)>;
3162+
def PseudoVSPILL_M8 : VPseudo<VS8R_V, V_M8, (outs), (ins VRM8:$rs1, GPR:$rs2)>;
3163+
}
3164+
3165+
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1 in {
3166+
def PseudoVRELOAD_M1 : VPseudo<VL1RE8_V, V_M1, (outs VR:$rs1), (ins GPR:$rs2)>;
3167+
def PseudoVRELOAD_M2 : VPseudo<VL2RE8_V, V_M2, (outs VRM2:$rs1), (ins GPR:$rs2)>;
3168+
def PseudoVRELOAD_M4 : VPseudo<VL4RE8_V, V_M4, (outs VRM4:$rs1), (ins GPR:$rs2)>;
3169+
def PseudoVRELOAD_M8 : VPseudo<VL8RE8_V, V_M8, (outs VRM8:$rs1), (ins GPR:$rs2)>;
3170+
}
3171+
31583172
//===----------------------------------------------------------------------===//
31593173
// 6. Configuration-Setting Instructions
31603174
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll

Lines changed: 87 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,87 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d -mattr=+d -O0 < %s \
3+
; RUN: | FileCheck --check-prefix=SPILL-O0 %s
4+
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d -mattr=+d -O2 < %s \
5+
; RUN: | FileCheck --check-prefix=SPILL-O2 %s
6+
7+
@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
8+
9+
define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double> %b, <vscale x 1 x double> %c, i32 %gvl) nounwind
10+
; SPILL-O0-LABEL: foo:
11+
; SPILL-O0: # %bb.0:
12+
; SPILL-O0-NEXT: addi sp, sp, -16
13+
; SPILL-O0-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
14+
; SPILL-O0-NEXT: csrr a1, vlenb
15+
; SPILL-O0-NEXT: slli a1, a1, 1
16+
; SPILL-O0-NEXT: sub sp, sp, a1
17+
; SPILL-O0-NEXT: csrr a1, vlenb
18+
; SPILL-O0-NEXT: slli a1, a1, 1
19+
; SPILL-O0-NEXT: add a1, sp, a1
20+
; SPILL-O0-NEXT: sw a0, 8(a1) # 4-byte Folded Spill
21+
; SPILL-O0-NEXT: csrr a1, vlenb
22+
; SPILL-O0-NEXT: add a1, sp, a1
23+
; SPILL-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
24+
; SPILL-O0-NEXT: vsetvli a0, a0, e64,m1,ta,mu
25+
; SPILL-O0-NEXT: vfadd.vv v25, v8, v9
26+
; SPILL-O0-NEXT: vs1r.v v25, (sp) # Unknown-size Folded Spill
27+
; SPILL-O0-NEXT: lui a0, %hi(.L.str)
28+
; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str)
29+
; SPILL-O0-NEXT: call puts@plt
30+
; SPILL-O0-NEXT: vl1r.v v25, (sp) # Unknown-size Folded Reload
31+
; SPILL-O0-NEXT: csrr a1, vlenb
32+
; SPILL-O0-NEXT: add a1, sp, a1
33+
; SPILL-O0-NEXT: vl1r.v v8, (a1) # Unknown-size Folded Reload
34+
; SPILL-O0-NEXT: # kill: def $x11 killed $x10
35+
; SPILL-O0-NEXT: csrr a0, vlenb
36+
; SPILL-O0-NEXT: slli a0, a0, 1
37+
; SPILL-O0-NEXT: add a0, sp, a0
38+
; SPILL-O0-NEXT: lw a0, 8(a0) # 4-byte Folded Reload
39+
; SPILL-O0-NEXT: vsetvli a0, a0, e64,m1,ta,mu
40+
; SPILL-O0-NEXT: vfadd.vv v8, v8, v25
41+
; SPILL-O0-NEXT: csrr a0, vlenb
42+
; SPILL-O0-NEXT: slli a0, a0, 1
43+
; SPILL-O0-NEXT: add sp, sp, a0
44+
; SPILL-O0-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
45+
; SPILL-O0-NEXT: addi sp, sp, 16
46+
; SPILL-O0-NEXT: ret
47+
;
48+
; SPILL-O2-LABEL: foo:
49+
; SPILL-O2: # %bb.0:
50+
; SPILL-O2-NEXT: addi sp, sp, -16
51+
; SPILL-O2-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
52+
; SPILL-O2-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
53+
; SPILL-O2-NEXT: csrr a1, vlenb
54+
; SPILL-O2-NEXT: slli a1, a1, 1
55+
; SPILL-O2-NEXT: sub sp, sp, a1
56+
; SPILL-O2-NEXT: mv s0, a0
57+
; SPILL-O2-NEXT: vs1r.v v8, (sp) # Unknown-size Folded Spill
58+
; SPILL-O2-NEXT: vsetvli a0, a0, e64,m1,ta,mu
59+
; SPILL-O2-NEXT: vfadd.vv v25, v8, v9
60+
; SPILL-O2-NEXT: csrr a0, vlenb
61+
; SPILL-O2-NEXT: add a0, sp, a0
62+
; SPILL-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
63+
; SPILL-O2-NEXT: lui a0, %hi(.L.str)
64+
; SPILL-O2-NEXT: addi a0, a0, %lo(.L.str)
65+
; SPILL-O2-NEXT: call puts@plt
66+
; SPILL-O2-NEXT: vsetvli a0, s0, e64,m1,ta,mu
67+
; SPILL-O2-NEXT: csrr a0, vlenb
68+
; SPILL-O2-NEXT: add a0, sp, a0
69+
; SPILL-O2-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload
70+
; SPILL-O2-NEXT: vl1r.v v26, (sp) # Unknown-size Folded Reload
71+
; SPILL-O2-NEXT: vfadd.vv v8, v26, v25
72+
; SPILL-O2-NEXT: csrr a0, vlenb
73+
; SPILL-O2-NEXT: slli a0, a0, 1
74+
; SPILL-O2-NEXT: add sp, sp, a0
75+
; SPILL-O2-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
76+
; SPILL-O2-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
77+
; SPILL-O2-NEXT: addi sp, sp, 16
78+
; SPILL-O2-NEXT: ret
79+
{
80+
%x = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 %gvl)
81+
%call = call signext i32 @puts(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0))
82+
%z = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %x, i32 %gvl)
83+
ret <vscale x 1 x double> %z
84+
}
85+
86+
declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 %gvl)
87+
declare i32 @puts(i8*);

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