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Rename to *Legacy
1 parent 5719569 commit a3d67dd

13 files changed

+36
-36
lines changed

‎llvm/include/llvm/CodeGen/VirtRegMap.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -190,13 +190,13 @@ inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) {
190190
return OS;
191191
}
192192

193-
class VirtRegMapWrapperPass : public MachineFunctionPass {
193+
class VirtRegMapWrapperLegacy : public MachineFunctionPass {
194194
VirtRegMap VRM;
195195

196196
public:
197197
static char ID;
198198

199-
VirtRegMapWrapperPass() : MachineFunctionPass(ID) {}
199+
VirtRegMapWrapperLegacy() : MachineFunctionPass(ID) {}
200200

201201
void print(raw_ostream &OS, const Module *M = nullptr) const override {
202202
VRM.print(OS, M);

‎llvm/include/llvm/InitializePasses.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -314,7 +314,7 @@ void initializeUnpackMachineBundlesPass(PassRegistry &);
314314
void initializeUnreachableBlockElimLegacyPassPass(PassRegistry &);
315315
void initializeUnreachableMachineBlockElimPass(PassRegistry &);
316316
void initializeVerifierLegacyPassPass(PassRegistry &);
317-
void initializeVirtRegMapWrapperPassPass(PassRegistry &);
317+
void initializeVirtRegMapWrapperLegacyPass(PassRegistry &);
318318
void initializeVirtRegRewriterPass(PassRegistry &);
319319
void initializeWasmEHPreparePass(PassRegistry &);
320320
void initializeWinEHPreparePass(PassRegistry &);

‎llvm/lib/CodeGen/CodeGen.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
138138
initializeUnpackMachineBundlesPass(Registry);
139139
initializeUnreachableBlockElimLegacyPassPass(Registry);
140140
initializeUnreachableMachineBlockElimPass(Registry);
141-
initializeVirtRegMapWrapperPassPass(Registry);
141+
initializeVirtRegMapWrapperLegacyPass(Registry);
142142
initializeVirtRegRewriterPass(Registry);
143143
initializeWasmEHPreparePass(Registry);
144144
initializeWinEHPreparePass(Registry);

‎llvm/lib/CodeGen/LiveRegMatrix.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ char LiveRegMatrix::ID = 0;
3939
INITIALIZE_PASS_BEGIN(LiveRegMatrix, "liveregmatrix",
4040
"Live Register Matrix", false, false)
4141
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
42-
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperPass)
42+
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
4343
INITIALIZE_PASS_END(LiveRegMatrix, "liveregmatrix",
4444
"Live Register Matrix", false, false)
4545

@@ -48,14 +48,14 @@ LiveRegMatrix::LiveRegMatrix() : MachineFunctionPass(ID) {}
4848
void LiveRegMatrix::getAnalysisUsage(AnalysisUsage &AU) const {
4949
AU.setPreservesAll();
5050
AU.addRequiredTransitive<LiveIntervalsWrapperPass>();
51-
AU.addRequiredTransitive<VirtRegMapWrapperPass>();
51+
AU.addRequiredTransitive<VirtRegMapWrapperLegacy>();
5252
MachineFunctionPass::getAnalysisUsage(AU);
5353
}
5454

5555
bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) {
5656
TRI = MF.getSubtarget().getRegisterInfo();
5757
LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
58-
VRM = &getAnalysis<VirtRegMapWrapperPass>().getVRM();
58+
VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
5959

6060
unsigned NumRegUnits = TRI->getNumRegUnits();
6161
if (NumRegUnits != Matrix.size())

‎llvm/lib/CodeGen/RegAllocBasic.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveStacks)
138138
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
139139
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
140140
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
141-
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperPass)
141+
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
142142
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
143143
INITIALIZE_PASS_END(RABasic, "regallocbasic", "Basic Register Allocator", false,
144144
false)
@@ -188,8 +188,8 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
188188
AU.addPreservedID(MachineDominatorsID);
189189
AU.addRequired<MachineLoopInfoWrapperPass>();
190190
AU.addPreserved<MachineLoopInfoWrapperPass>();
191-
AU.addRequired<VirtRegMapWrapperPass>();
192-
AU.addPreserved<VirtRegMapWrapperPass>();
191+
AU.addRequired<VirtRegMapWrapperLegacy>();
192+
AU.addPreserved<VirtRegMapWrapperLegacy>();
193193
AU.addRequired<LiveRegMatrix>();
194194
AU.addPreserved<LiveRegMatrix>();
195195
MachineFunctionPass::getAnalysisUsage(AU);
@@ -307,7 +307,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
307307
<< "********** Function: " << mf.getName() << '\n');
308308

309309
MF = &mf;
310-
RegAllocBase::init(getAnalysis<VirtRegMapWrapperPass>().getVRM(),
310+
RegAllocBase::init(getAnalysis<VirtRegMapWrapperLegacy>().getVRM(),
311311
getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
312312
getAnalysis<LiveRegMatrix>());
313313
VirtRegAuxInfo VRAI(

‎llvm/lib/CodeGen/RegAllocGreedy.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,7 @@ INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
162162
INITIALIZE_PASS_DEPENDENCY(LiveStacks)
163163
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
164164
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
165-
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperPass)
165+
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
166166
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
167167
INITIALIZE_PASS_DEPENDENCY(EdgeBundles)
168168
INITIALIZE_PASS_DEPENDENCY(SpillPlacement)
@@ -215,8 +215,8 @@ void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
215215
AU.addPreserved<MachineDominatorTreeWrapperPass>();
216216
AU.addRequired<MachineLoopInfoWrapperPass>();
217217
AU.addPreserved<MachineLoopInfoWrapperPass>();
218-
AU.addRequired<VirtRegMapWrapperPass>();
219-
AU.addPreserved<VirtRegMapWrapperPass>();
218+
AU.addRequired<VirtRegMapWrapperLegacy>();
219+
AU.addPreserved<VirtRegMapWrapperLegacy>();
220220
AU.addRequired<LiveRegMatrix>();
221221
AU.addPreserved<LiveRegMatrix>();
222222
AU.addRequired<EdgeBundles>();
@@ -2716,7 +2716,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
27162716
if (VerifyEnabled)
27172717
MF->verify(this, "Before greedy register allocator", &errs());
27182718

2719-
RegAllocBase::init(getAnalysis<VirtRegMapWrapperPass>().getVRM(),
2719+
RegAllocBase::init(getAnalysis<VirtRegMapWrapperLegacy>().getVRM(),
27202720
getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
27212721
getAnalysis<LiveRegMatrix>());
27222722

‎llvm/lib/CodeGen/RegAllocPBQP.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,7 @@ class RegAllocPBQP : public MachineFunctionPass {
123123
initializeSlotIndexesWrapperPassPass(*PassRegistry::getPassRegistry());
124124
initializeLiveIntervalsWrapperPassPass(*PassRegistry::getPassRegistry());
125125
initializeLiveStacksPass(*PassRegistry::getPassRegistry());
126-
initializeVirtRegMapWrapperPassPass(*PassRegistry::getPassRegistry());
126+
initializeVirtRegMapWrapperLegacyPass(*PassRegistry::getPassRegistry());
127127
}
128128

129129
/// Return the pass name.
@@ -559,8 +559,8 @@ void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
559559
au.addPreserved<MachineLoopInfoWrapperPass>();
560560
au.addRequired<MachineDominatorTreeWrapperPass>();
561561
au.addPreserved<MachineDominatorTreeWrapperPass>();
562-
au.addRequired<VirtRegMapWrapperPass>();
563-
au.addPreserved<VirtRegMapWrapperPass>();
562+
au.addRequired<VirtRegMapWrapperLegacy>();
563+
au.addPreserved<VirtRegMapWrapperLegacy>();
564564
MachineFunctionPass::getAnalysisUsage(au);
565565
}
566566

@@ -795,7 +795,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
795795
MachineBlockFrequencyInfo &MBFI =
796796
getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
797797

798-
VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperPass>().getVRM();
798+
VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
799799

800800
PBQPVirtRegAuxInfo VRAI(
801801
MF, LIS, VRM, getAnalysis<MachineLoopInfoWrapperPass>().getLI(), MBFI);

‎llvm/lib/CodeGen/VirtRegMap.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -56,9 +56,9 @@ STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
5656
// VirtRegMap implementation
5757
//===----------------------------------------------------------------------===//
5858

59-
char VirtRegMapWrapperPass::ID = 0;
59+
char VirtRegMapWrapperLegacy::ID = 0;
6060

61-
INITIALIZE_PASS(VirtRegMapWrapperPass, "virtregmap", "Virtual Register Map",
61+
INITIALIZE_PASS(VirtRegMapWrapperLegacy, "virtregmap", "Virtual Register Map",
6262
false, false)
6363

6464
void VirtRegMap::init(MachineFunction &mf) {
@@ -248,7 +248,7 @@ INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
248248
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
249249
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
250250
INITIALIZE_PASS_DEPENDENCY(LiveStacks)
251-
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperPass)
251+
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
252252
INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
253253
"Virtual Register Rewriter", false, false)
254254

@@ -261,7 +261,7 @@ void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
261261
AU.addRequired<LiveDebugVariables>();
262262
AU.addRequired<LiveStacks>();
263263
AU.addPreserved<LiveStacks>();
264-
AU.addRequired<VirtRegMapWrapperPass>();
264+
AU.addRequired<VirtRegMapWrapperLegacy>();
265265

266266
if (!ClearVirtRegs)
267267
AU.addPreserved<LiveDebugVariables>();
@@ -276,7 +276,7 @@ bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
276276
MRI = &MF->getRegInfo();
277277
Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
278278
LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
279-
VRM = &getAnalysis<VirtRegMapWrapperPass>().getVRM();
279+
VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
280280
DebugVars = &getAnalysis<LiveDebugVariables>();
281281
LLVM_DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
282282
<< "********** Function: " << MF->getName() << '\n');

‎llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ class GCNNSAReassign : public MachineFunctionPass {
4949

5050
void getAnalysisUsage(AnalysisUsage &AU) const override {
5151
AU.addRequired<LiveIntervalsWrapperPass>();
52-
AU.addRequired<VirtRegMapWrapperPass>();
52+
AU.addRequired<VirtRegMapWrapperLegacy>();
5353
AU.addRequired<LiveRegMatrix>();
5454
AU.setPreservesAll();
5555
MachineFunctionPass::getAnalysisUsage(AU);
@@ -95,7 +95,7 @@ class GCNNSAReassign : public MachineFunctionPass {
9595
INITIALIZE_PASS_BEGIN(GCNNSAReassign, DEBUG_TYPE, "GCN NSA Reassign",
9696
false, false)
9797
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
98-
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperPass)
98+
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
9999
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
100100
INITIALIZE_PASS_END(GCNNSAReassign, DEBUG_TYPE, "GCN NSA Reassign",
101101
false, false)
@@ -242,7 +242,7 @@ bool GCNNSAReassign::runOnMachineFunction(MachineFunction &MF) {
242242

243243
MRI = &MF.getRegInfo();
244244
TRI = ST->getRegisterInfo();
245-
VRM = &getAnalysis<VirtRegMapWrapperPass>().getVRM();
245+
VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
246246
LRM = &getAnalysis<LiveRegMatrix>();
247247
LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
248248

‎llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ char SILowerSGPRSpillsLegacy::ID = 0;
9595
INITIALIZE_PASS_BEGIN(SILowerSGPRSpillsLegacy, DEBUG_TYPE,
9696
"SI lower SGPR spill instructions", false, false)
9797
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
98-
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperPass)
98+
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
9999
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
100100
INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE,
101101
"SI lower SGPR spill instructions", false, false)

‎llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ class SILowerWWMCopies : public MachineFunctionPass {
6464
INITIALIZE_PASS_BEGIN(SILowerWWMCopies, DEBUG_TYPE, "SI Lower WWM Copies",
6565
false, false)
6666
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
67-
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperPass)
67+
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
6868
INITIALIZE_PASS_END(SILowerWWMCopies, DEBUG_TYPE, "SI Lower WWM Copies", false,
6969
false)
7070

@@ -105,7 +105,7 @@ bool SILowerWWMCopies::runOnMachineFunction(MachineFunction &MF) {
105105
LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
106106
auto *SIWrapper = getAnalysisIfAvailable<SlotIndexesWrapperPass>();
107107
Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr;
108-
auto *VRMWrapper = getAnalysisIfAvailable<VirtRegMapWrapperPass>();
108+
auto *VRMWrapper = getAnalysisIfAvailable<VirtRegMapWrapperLegacy>();
109109
VRM = VRMWrapper ? &VRMWrapper->getVRM() : nullptr;
110110
TRI = ST.getRegisterInfo();
111111
MRI = &MF.getRegInfo();

‎llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ class SIPreAllocateWWMRegs : public MachineFunctionPass {
6060

6161
void getAnalysisUsage(AnalysisUsage &AU) const override {
6262
AU.addRequired<LiveIntervalsWrapperPass>();
63-
AU.addRequired<VirtRegMapWrapperPass>();
63+
AU.addRequired<VirtRegMapWrapperLegacy>();
6464
AU.addRequired<LiveRegMatrix>();
6565
AU.setPreservesAll();
6666
MachineFunctionPass::getAnalysisUsage(AU);
@@ -76,7 +76,7 @@ class SIPreAllocateWWMRegs : public MachineFunctionPass {
7676
INITIALIZE_PASS_BEGIN(SIPreAllocateWWMRegs, DEBUG_TYPE,
7777
"SI Pre-allocate WWM Registers", false, false)
7878
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
79-
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperPass)
79+
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
8080
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
8181
INITIALIZE_PASS_END(SIPreAllocateWWMRegs, DEBUG_TYPE,
8282
"SI Pre-allocate WWM Registers", false, false)
@@ -195,7 +195,7 @@ bool SIPreAllocateWWMRegs::runOnMachineFunction(MachineFunction &MF) {
195195

196196
LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
197197
Matrix = &getAnalysis<LiveRegMatrix>();
198-
VRM = &getAnalysis<VirtRegMapWrapperPass>().getVRM();
198+
VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
199199

200200
RegClassInfo.runOnMachineFunction(MF);
201201

‎llvm/lib/Target/X86/X86TileConfig.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ struct X86TileConfig : public MachineFunctionPass {
5050
/// X86TileConfig analysis usage.
5151
void getAnalysisUsage(AnalysisUsage &AU) const override {
5252
AU.setPreservesAll();
53-
AU.addRequired<VirtRegMapWrapperPass>();
53+
AU.addRequired<VirtRegMapWrapperLegacy>();
5454
AU.addRequired<LiveIntervalsWrapperPass>();
5555
MachineFunctionPass::getAnalysisUsage(AU);
5656
}
@@ -72,7 +72,7 @@ char X86TileConfig::ID = 0;
7272

7373
INITIALIZE_PASS_BEGIN(X86TileConfig, DEBUG_TYPE, "Tile Register Configure",
7474
false, false)
75-
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperPass)
75+
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
7676
INITIALIZE_PASS_END(X86TileConfig, DEBUG_TYPE, "Tile Register Configure", false,
7777
false)
7878

@@ -87,7 +87,7 @@ bool X86TileConfig::runOnMachineFunction(MachineFunction &MF) {
8787
const TargetInstrInfo *TII = ST.getInstrInfo();
8888
MachineRegisterInfo &MRI = MF.getRegInfo();
8989
LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
90-
VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperPass>().getVRM();
90+
VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
9191

9292
if (VRM.isShapeMapEmpty())
9393
return false;

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