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move isRenamedInGFX9 to be static and add helper macro for case prefixes
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2 files changed

+17
-56
lines changed

2 files changed

+17
-56
lines changed

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 17 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -9115,68 +9115,31 @@ bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const {
91159115
}
91169116
}
91179117

9118-
bool SIInstrInfo::isRenamedInGFX9(int Opcode) const {
9118+
#define GENERATE_RENAMED_GFX9_CASES(OPCODE) \
9119+
case OPCODE##_dpp: \
9120+
case OPCODE##_e32: \
9121+
case OPCODE##_e64: \
9122+
case OPCODE##_e64_dpp: \
9123+
case OPCODE##_sdwa:
9124+
9125+
static bool isRenamedInGFX9(int Opcode) {
91199126
switch (Opcode) {
9120-
case AMDGPU::V_ADDC_U32_dpp:
9121-
case AMDGPU::V_ADDC_U32_e32:
9122-
case AMDGPU::V_ADDC_U32_e64:
9123-
case AMDGPU::V_ADDC_U32_e64_dpp:
9124-
case AMDGPU::V_ADDC_U32_sdwa:
9125-
//
9126-
case AMDGPU::V_ADD_CO_U32_dpp:
9127-
case AMDGPU::V_ADD_CO_U32_e32:
9128-
case AMDGPU::V_ADD_CO_U32_e64:
9129-
case AMDGPU::V_ADD_CO_U32_e64_dpp:
9130-
case AMDGPU::V_ADD_CO_U32_sdwa:
9131-
//
9132-
case AMDGPU::V_ADD_U32_dpp:
9133-
case AMDGPU::V_ADD_U32_e32:
9134-
case AMDGPU::V_ADD_U32_e64:
9135-
case AMDGPU::V_ADD_U32_e64_dpp:
9136-
case AMDGPU::V_ADD_U32_sdwa:
9127+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_ADDC_U32)
9128+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_ADD_CO_U32)
9129+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_ADD_U32)
9130+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUBBREV_U32)
9131+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUBB_U32)
9132+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUBREV_CO_U32)
9133+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUBREV_U32)
9134+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUB_CO_U32)
9135+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUB_U32)
91379136
//
91389137
case AMDGPU::V_DIV_FIXUP_F16_gfx9_e64:
91399138
case AMDGPU::V_FMA_F16_gfx9_e64:
91409139
case AMDGPU::V_INTERP_P2_F16:
91419140
case AMDGPU::V_MAD_F16_e64:
91429141
case AMDGPU::V_MAD_U16_e64:
91439142
case AMDGPU::V_MAD_I16_e64:
9144-
//
9145-
case AMDGPU::V_SUBBREV_U32_dpp:
9146-
case AMDGPU::V_SUBBREV_U32_e32:
9147-
case AMDGPU::V_SUBBREV_U32_e64:
9148-
case AMDGPU::V_SUBBREV_U32_e64_dpp:
9149-
case AMDGPU::V_SUBBREV_U32_sdwa:
9150-
//
9151-
case AMDGPU::V_SUBB_U32_dpp:
9152-
case AMDGPU::V_SUBB_U32_e32:
9153-
case AMDGPU::V_SUBB_U32_e64:
9154-
case AMDGPU::V_SUBB_U32_e64_dpp:
9155-
case AMDGPU::V_SUBB_U32_sdwa:
9156-
//
9157-
case AMDGPU::V_SUBREV_CO_U32_dpp:
9158-
case AMDGPU::V_SUBREV_CO_U32_e32:
9159-
case AMDGPU::V_SUBREV_CO_U32_e64:
9160-
case AMDGPU::V_SUBREV_CO_U32_e64_dpp:
9161-
case AMDGPU::V_SUBREV_CO_U32_sdwa:
9162-
//
9163-
case AMDGPU::V_SUBREV_U32_dpp:
9164-
case AMDGPU::V_SUBREV_U32_e32:
9165-
case AMDGPU::V_SUBREV_U32_e64:
9166-
case AMDGPU::V_SUBREV_U32_e64_dpp:
9167-
case AMDGPU::V_SUBREV_U32_sdwa:
9168-
//
9169-
case AMDGPU::V_SUB_CO_U32_dpp:
9170-
case AMDGPU::V_SUB_CO_U32_e32:
9171-
case AMDGPU::V_SUB_CO_U32_e64:
9172-
case AMDGPU::V_SUB_CO_U32_e64_dpp:
9173-
case AMDGPU::V_SUB_CO_U32_sdwa:
9174-
//
9175-
case AMDGPU::V_SUB_U32_dpp:
9176-
case AMDGPU::V_SUB_U32_e32:
9177-
case AMDGPU::V_SUB_U32_e64:
9178-
case AMDGPU::V_SUB_U32_e64_dpp:
9179-
case AMDGPU::V_SUB_U32_sdwa:
91809143
return true;
91819144
default:
91829145
return false;

llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1339,8 +1339,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
13391339
/// Return true if this opcode should not be used by codegen.
13401340
bool isAsmOnlyOpcode(int MCOp) const;
13411341

1342-
bool isRenamedInGFX9(int Opcode) const;
1343-
13441342
const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
13451343
const TargetRegisterInfo *TRI,
13461344
const MachineFunction &MF)

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