[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)

This reverts commit 201f892.

Author: jayfoad

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

@@ -717,24 +717,6 @@ void SIFoldOperands::foldOperand(
 
     const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg);
     if (!DestReg.isPhysical()) {
-      if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) {
-        SmallVector<FoldCandidate, 4> CopyUses;
-        for (auto &Use : MRI->use_nodbg_operands(DestReg)) {
-          // There's no point trying to fold into an implicit operand.
-          if (Use.isImplicit())
-            continue;
-
-          CopyUses.emplace_back(Use.getParent(),
-                                Use.getParent()->getOperandNo(&Use),
-                                &UseMI->getOperand(1));
-        }
-
-        for (auto &F : CopyUses) {
-          foldOperand(*F.OpToFold, F.UseMI, F.UseOpNo, FoldList,
-                      CopiesToReplace);
-        }
-      }
-
       if (DestRC == &AMDGPU::AGPR_32RegClass &&
           TII->isInlineConstant(OpToFold, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {
         UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64));

llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll

@@ -165,9 +165,8 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_splat(<2 x i16> %a) {
 ; GFX7-LABEL: v_add_v2i16_neg_inline_imm_splat:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    s_movk_i32 s4, 0xffc0
-; GFX7-NEXT:    v_add_i32_e32 v0, vcc, s4, v0
-; GFX7-NEXT:    v_add_i32_e32 v1, vcc, s4, v1
+; GFX7-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffc0, v0
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, 0xffffffc0, v1
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_add_v2i16_neg_inline_imm_splat:
@@ -180,10 +179,10 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_splat(<2 x i16> %a) {
 ; GFX8-LABEL: v_add_v2i16_neg_inline_imm_splat:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_mov_b32_e32 v2, 0xffffffc0
-; GFX8-NEXT:    v_add_u16_e32 v1, 0xffc0, v0
-; GFX8-NEXT:    v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT:    v_mov_b32_e32 v1, 0xffffffc0
+; GFX8-NEXT:    v_add_u16_e32 v2, 0xffc0, v0
+; GFX8-NEXT:    v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_add_v2i16_neg_inline_imm_splat:

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll

@@ -126,14 +126,13 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
 ; GFX6-LABEL: v_pow_v2f32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    s_mov_b32 s4, 0x800000
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0x4f800000
-; GFX6-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
-; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v5
-; GFX6-NEXT:    v_mov_b32_e32 v5, 0x800000
-; GFX6-NEXT:    v_cmp_lt_f32_e64 s[4:5], v1, v5
-; GFX6-NEXT:    v_cndmask_b32_e64 v4, 1.0, v4, s[4:5]
+; GFX6-NEXT:    v_mov_b32_e32 v4, 0x800000
+; GFX6-NEXT:    v_mov_b32_e32 v5, 0x4f800000
+; GFX6-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v6, 1.0, v5, vcc
+; GFX6-NEXT:    v_cmp_lt_f32_e64 s[4:5], v1, v4
+; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v6
+; GFX6-NEXT:    v_cndmask_b32_e64 v4, 1.0, v5, s[4:5]
 ; GFX6-NEXT:    v_log_f32_e32 v0, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v1, v4
 ; GFX6-NEXT:    v_log_f32_e32 v1, v1
@@ -142,15 +141,15 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
 ; GFX6-NEXT:    v_sub_f32_e32 v0, v0, v7
 ; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, v6, s[4:5]
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v2
-; GFX6-NEXT:    s_mov_b32 s6, 0xc2fc0000
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0xc2fc0000
 ; GFX6-NEXT:    v_sub_f32_e32 v1, v1, v5
-; GFX6-NEXT:    v_mov_b32_e32 v2, 0x42800000
-; GFX6-NEXT:    v_cmp_gt_f32_e32 vcc, s6, v0
+; GFX6-NEXT:    v_mov_b32_e32 v7, 0x42800000
+; GFX6-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v1, v1, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v7, 0, v2, vcc
-; GFX6-NEXT:    v_cmp_gt_f32_e64 s[4:5], s6, v1
-; GFX6-NEXT:    v_add_f32_e32 v0, v0, v7
-; GFX6-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s[4:5]
+; GFX6-NEXT:    v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX6-NEXT:    v_cmp_lt_f32_e64 s[4:5], v1, v2
+; GFX6-NEXT:    v_add_f32_e32 v0, v0, v8
+; GFX6-NEXT:    v_cndmask_b32_e64 v2, 0, v7, s[4:5]
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX6-NEXT:    v_exp_f32_e32 v1, v1
@@ -164,14 +163,13 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
 ; GFX8-LABEL: v_pow_v2f32:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    s_mov_b32 s4, 0x800000
-; GFX8-NEXT:    v_mov_b32_e32 v4, 0x4f800000
-; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX8-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
-; GFX8-NEXT:    v_mul_f32_e32 v0, v0, v5
-; GFX8-NEXT:    v_mov_b32_e32 v5, 0x800000
-; GFX8-NEXT:    v_cmp_lt_f32_e64 s[4:5], v1, v5
-; GFX8-NEXT:    v_cndmask_b32_e64 v4, 1.0, v4, s[4:5]
+; GFX8-NEXT:    v_mov_b32_e32 v4, 0x800000
+; GFX8-NEXT:    v_mov_b32_e32 v5, 0x4f800000
+; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v4
+; GFX8-NEXT:    v_cndmask_b32_e32 v6, 1.0, v5, vcc
+; GFX8-NEXT:    v_cmp_lt_f32_e64 s[4:5], v1, v4
+; GFX8-NEXT:    v_mul_f32_e32 v0, v0, v6
+; GFX8-NEXT:    v_cndmask_b32_e64 v4, 1.0, v5, s[4:5]
 ; GFX8-NEXT:    v_log_f32_e32 v0, v0
 ; GFX8-NEXT:    v_mul_f32_e32 v1, v1, v4
 ; GFX8-NEXT:    v_log_f32_e32 v1, v1
@@ -180,15 +178,15 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
 ; GFX8-NEXT:    v_sub_f32_e32 v0, v0, v7
 ; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, v6, s[4:5]
 ; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, v0, v2
-; GFX8-NEXT:    s_mov_b32 s6, 0xc2fc0000
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0xc2fc0000
 ; GFX8-NEXT:    v_sub_f32_e32 v1, v1, v5
-; GFX8-NEXT:    v_mov_b32_e32 v2, 0x42800000
-; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, s6, v0
+; GFX8-NEXT:    v_mov_b32_e32 v7, 0x42800000
+; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX8-NEXT:    v_mul_legacy_f32_e32 v1, v1, v3
-; GFX8-NEXT:    v_cndmask_b32_e32 v7, 0, v2, vcc
-; GFX8-NEXT:    v_cmp_gt_f32_e64 s[4:5], s6, v1
-; GFX8-NEXT:    v_add_f32_e32 v0, v0, v7
-; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s[4:5]
+; GFX8-NEXT:    v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX8-NEXT:    v_cmp_lt_f32_e64 s[4:5], v1, v2
+; GFX8-NEXT:    v_add_f32_e32 v0, v0, v8
+; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, v7, s[4:5]
 ; GFX8-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX8-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX8-NEXT:    v_exp_f32_e32 v1, v1
@@ -202,14 +200,13 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
 ; GFX9-LABEL: v_pow_v2f32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    s_mov_b32 s4, 0x800000
-; GFX9-NEXT:    v_mov_b32_e32 v4, 0x4f800000
-; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX9-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
-; GFX9-NEXT:    v_mul_f32_e32 v0, v0, v5
-; GFX9-NEXT:    v_mov_b32_e32 v5, 0x800000
-; GFX9-NEXT:    v_cmp_lt_f32_e64 s[4:5], v1, v5
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, 1.0, v4, s[4:5]
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0x800000
+; GFX9-NEXT:    v_mov_b32_e32 v5, 0x4f800000
+; GFX9-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v4
+; GFX9-NEXT:    v_cndmask_b32_e32 v6, 1.0, v5, vcc
+; GFX9-NEXT:    v_cmp_lt_f32_e64 s[4:5], v1, v4
+; GFX9-NEXT:    v_mul_f32_e32 v0, v0, v6
+; GFX9-NEXT:    v_cndmask_b32_e64 v4, 1.0, v5, s[4:5]
 ; GFX9-NEXT:    v_log_f32_e32 v0, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, v1, v4
 ; GFX9-NEXT:    v_log_f32_e32 v1, v1
@@ -218,15 +215,15 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
 ; GFX9-NEXT:    v_sub_f32_e32 v0, v0, v7
 ; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, v6, s[4:5]
 ; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, v0, v2
-; GFX9-NEXT:    s_mov_b32 s6, 0xc2fc0000
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0xc2fc0000
 ; GFX9-NEXT:    v_sub_f32_e32 v1, v1, v5
-; GFX9-NEXT:    v_mov_b32_e32 v2, 0x42800000
-; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, s6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, 0x42800000
+; GFX9-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX9-NEXT:    v_mul_legacy_f32_e32 v1, v1, v3
-; GFX9-NEXT:    v_cndmask_b32_e32 v7, 0, v2, vcc
-; GFX9-NEXT:    v_cmp_gt_f32_e64 s[4:5], s6, v1
-; GFX9-NEXT:    v_add_f32_e32 v0, v0, v7
-; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s[4:5]
+; GFX9-NEXT:    v_cndmask_b32_e32 v8, 0, v7, vcc
+; GFX9-NEXT:    v_cmp_lt_f32_e64 s[4:5], v1, v2
+; GFX9-NEXT:    v_add_f32_e32 v0, v0, v8
+; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, v7, s[4:5]
 ; GFX9-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX9-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX9-NEXT:    v_exp_f32_e32 v1, v1
@@ -382,25 +379,25 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
 ; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
 ; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT:    s_mov_b32 s4, 0xc2fc0000
+; GFX6-NEXT:    v_mov_b32_e32 v4, 0xc2fc0000
 ; GFX6-NEXT:    v_log_f32_e32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0x42800000
+; GFX6-NEXT:    v_mov_b32_e32 v5, 0x42800000
 ; GFX6-NEXT:    v_log_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v2
-; GFX6-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
+; GFX6-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
 ; GFX6-NEXT:    v_add_f32_e32 v0, v0, v2
 ; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v3
 ; GFX6-NEXT:    v_mov_b32_e32 v3, 0x1f800000
-; GFX6-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; GFX6-NEXT:    v_cndmask_b32_e32 v6, 1.0, v3, vcc
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v1, v1, v2
-; GFX6-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
+; GFX6-NEXT:    v_cmp_lt_f32_e32 vcc, v1, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
 ; GFX6-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX6-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
-; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v5
+; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v6
 ; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v1, v2
 ; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
@@ -505,22 +502,22 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
 ; GFX6-NEXT:    v_log_f32_e32 v1, v1
 ; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
 ; GFX6-NEXT:    v_log_f32_e32 v0, v0
-; GFX6-NEXT:    s_mov_b32 s4, 0xc2fc0000
+; GFX6-NEXT:    v_mov_b32_e32 v4, 0x42800000
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v1, v1, v2
-; GFX6-NEXT:    v_mov_b32_e32 v2, 0x42800000
-; GFX6-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v4, 0, v2, vcc
-; GFX6-NEXT:    v_add_f32_e32 v1, v1, v4
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0x1f800000
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0xc2fc0000
+; GFX6-NEXT:    v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v5, 0, v4, vcc
+; GFX6-NEXT:    v_add_f32_e32 v1, v1, v5
+; GFX6-NEXT:    v_mov_b32_e32 v5, 0x1f800000
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
-; GFX6-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT:    v_cndmask_b32_e32 v6, 1.0, v5, vcc
+; GFX6-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
 ; GFX6-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX6-NEXT:    v_add_f32_e32 v0, v0, v2
 ; GFX6-NEXT:    v_exp_f32_e32 v2, v0
-; GFX6-NEXT:    v_mul_f32_e32 v0, v1, v5
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, 1.0, v4, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v0, v1, v6
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, 1.0, v5, vcc
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
 ; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
@@ -632,21 +629,21 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
 ; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
 ; GFX6-NEXT:    v_log_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v3
-; GFX6-NEXT:    s_mov_b32 s4, 0xc2fc0000
-; GFX6-NEXT:    v_mov_b32_e32 v3, 0x42800000
-; GFX6-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v4, 0, v3, vcc
-; GFX6-NEXT:    v_add_f32_e32 v0, v0, v4
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0x1f800000
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0xc2fc0000
+; GFX6-NEXT:    v_mov_b32_e32 v4, 0x42800000
+; GFX6-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v5, 0, v4, vcc
+; GFX6-NEXT:    v_add_f32_e32 v0, v0, v5
+; GFX6-NEXT:    v_mov_b32_e32 v5, 0x1f800000
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v1, v1, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
-; GFX6-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX6-NEXT:    v_cndmask_b32_e32 v6, 1.0, v5, vcc
+; GFX6-NEXT:    v_cmp_lt_f32_e32 vcc, v1, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
 ; GFX6-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    v_exp_f32_e32 v1, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, 1.0, v4, vcc
-; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v5
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 1.0, v5, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v6
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v1, v2
 ; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
@@ -762,21 +759,21 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
 ; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; GFX6-NEXT:    v_log_f32_e32 v0, v0
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v2, v3, v2
-; GFX6-NEXT:    s_mov_b32 s4, 0xc2fc0000
-; GFX6-NEXT:    v_mov_b32_e32 v3, 0x42800000
-; GFX6-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v4, 0, v3, vcc
-; GFX6-NEXT:    v_add_f32_e32 v2, v2, v4
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0x1f800000
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0xc2fc0000
+; GFX6-NEXT:    v_mov_b32_e32 v4, 0x42800000
+; GFX6-NEXT:    v_cmp_lt_f32_e32 vcc, v2, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v5, 0, v4, vcc
+; GFX6-NEXT:    v_add_f32_e32 v2, v2, v5
+; GFX6-NEXT:    v_mov_b32_e32 v5, 0x1f800000
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
-; GFX6-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
+; GFX6-NEXT:    v_cndmask_b32_e32 v6, 1.0, v5, vcc
+; GFX6-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
 ; GFX6-NEXT:    v_exp_f32_e32 v2, v2
 ; GFX6-NEXT:    v_add_f32_e32 v0, v0, v1
 ; GFX6-NEXT:    v_exp_f32_e32 v1, v0
-; GFX6-NEXT:    v_mul_f32_e32 v0, v2, v5
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, 1.0, v4, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v0, v2, v6
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 1.0, v5, vcc
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v1, v2
 ; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1