[ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing

This changs the way the assembly matcher works for Aarch32 parsing.
Previously there  was a pile of hacks which dictated whether the CC
and CCOut operands should be present which de-facto chose if the
wide/narrow (or thumb1/thumb2/arm) instruction version were chosen.

This meant much of the TableGen machinery present for the assembly
matching was effectively being bypassed and worked around.

This patch makes the CC and CCOut operands optional which allows
the ASM matcher operate as it was designed and means we can avoid
doing some of the hacks done previously. This also adds the option
for the target to allow the prioritizing the smaller instruction
encodings as is required for Aarch32.

Author: AlfieRichardsArm

llvm/include/llvm/Target/Target.td

@@ -948,9 +948,18 @@ class AsmOperandClass {
   /// error will be suppressed if all of the remaining unmatched operands are
   /// marked as IsOptional.
   ///
-  /// Optional arguments must be at the end of the operand list.
+  /// Note: Optional arguments have caveats if they are not at the end of this list
+  /// when regarding custom operand parsing. See below
   bit IsOptional = false;
 
+  // Fixme: Ideally this would not be necessary however this would involve interleaving the
+  // parsing and matching processes.
+  /// Set to 1 if the parser should assume this operand will always be present
+  /// for the sake of calculating the operand index in regards to which custom operand
+  /// parser should be used.
+  /// This is only used for custom operands that are not at the end of the instruction.
+  bit OptionalShouldOffsetCustomParsers = true;
+
   /// The name of the method on the target specific asm parser that returns the
   /// default operand for this optional operand. This method is only used if
   /// IsOptional == 1. If not set, this will default to "defaultFooOperands",

llvm/lib/Target/ARM/ARM.td

@@ -1747,4 +1747,5 @@ def ARM : Target {
   let AssemblyParsers = [ARMAsmParser];
   let AssemblyParserVariants = [ARMAsmParserVariant];
   let AllowRegisterRenaming = 1;
+  let PreferSmallerInstructions= true;
 }

llvm/lib/Target/ARM/ARMInstrFormats.td

@@ -155,7 +155,13 @@ def iflags_op : Operand<i32> {
 
 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
 // register whose default is 0 (no register).
-def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
+def CondCodeOperand : AsmOperandClass {
+  let Name = "CondCode";
+  let PredicateMethod = "isCondCode";
+  let DefaultMethod = "defaultCondCodeOp";
+  let IsOptional = true;
+  let OptionalShouldOffsetCustomParsers = false;
+}
 def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
                                      (ops (i32 14), (i32 zero_reg))> {
   let PrintMethod = "printPredicateOperand";
@@ -174,7 +180,12 @@ def cmovpred : Operand<i32>, PredicateOp,
 }
 
 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
-def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
+def CCOutOperand : AsmOperandClass {
+  let Name = "CCOut";
+  let DefaultMethod = "defaultCCOutOp";
+  let IsOptional = true;
+  let OptionalShouldOffsetCustomParsers = false;
+}
 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
   let EncoderMethod = "getCCOutOpValue";
   let PrintMethod = "printSBitModifierOperand";
@@ -468,7 +479,7 @@ class InstThumb<AddrMode am, int sz, IndexMode im,
 // These are aliases that require C++ handling to convert to the target
 // instruction, while InstAliases can be handled directly by tblgen.
 class AsmPseudoInst<string asm, dag iops, dag oops = (outs)>
-  : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
+  : InstTemplate<AddrModeNone, 4, IndexModeNone, Pseudo, GenericDomain,
                  "", NoItinerary> {
   let OutOperandList = oops;
   let InOperandList = iops;