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michaelmaitlandmichaelmaitland
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[RISCV][VLOPT] Add floating point multiply divide instructions to getSupportedInstr
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3 files changed

+114
-16
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3 files changed

+114
-16
lines changed

‎llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -998,6 +998,12 @@ static bool isSupportedInstr(const MachineInstr &MI) {
998998
case RISCV::VFWADD_WV:
999999
case RISCV::VFWSUB_WF:
10001000
case RISCV::VFWSUB_WV:
1001+
// Vector Single-Width Floating-Point Multiply/Divide Instructions
1002+
case RISCV::VFMUL_VF:
1003+
case RISCV::VFMUL_VV:
1004+
case RISCV::VFDIV_VF:
1005+
case RISCV::VFDIV_VV:
1006+
case RISCV::VFRDIV_VF:
10011007
// Single-Width Floating-Point/Integer Type-Convert Instructions
10021008
case RISCV::VFCVT_XU_F_V:
10031009
case RISCV::VFCVT_X_F_V:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -363,12 +363,11 @@ define void @fmul_v6f16(ptr %x, ptr %y) {
363363
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
364364
; ZVFHMIN-NEXT: vle16.v v8, (a1)
365365
; ZVFHMIN-NEXT: vle16.v v9, (a0)
366-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
367366
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
368367
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
369368
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
370369
; ZVFHMIN-NEXT: vfmul.vv v8, v12, v10
371-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
370+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
372371
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
373372
; ZVFHMIN-NEXT: vse16.v v10, (a0)
374373
; ZVFHMIN-NEXT: ret
@@ -499,12 +498,11 @@ define void @fdiv_v6f16(ptr %x, ptr %y) {
499498
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
500499
; ZVFHMIN-NEXT: vle16.v v8, (a1)
501500
; ZVFHMIN-NEXT: vle16.v v9, (a0)
502-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
503501
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
504502
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
505503
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
506504
; ZVFHMIN-NEXT: vfdiv.vv v8, v12, v10
507-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
505+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
508506
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
509507
; ZVFHMIN-NEXT: vse16.v v10, (a0)
510508
; ZVFHMIN-NEXT: ret
@@ -2892,13 +2890,12 @@ define void @fmul_vf_v6f16(ptr %x, half %y) {
28922890
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
28932891
; ZVFHMIN-NEXT: vle16.v v8, (a0)
28942892
; ZVFHMIN-NEXT: fmv.x.w a1, fa0
2895-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
28962893
; ZVFHMIN-NEXT: vmv.v.x v9, a1
28972894
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
28982895
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
28992896
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
29002897
; ZVFHMIN-NEXT: vfmul.vv v8, v10, v12
2901-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
2898+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
29022899
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
29032900
; ZVFHMIN-NEXT: vse16.v v10, (a0)
29042901
; ZVFHMIN-NEXT: ret
@@ -3034,13 +3031,12 @@ define void @fmul_fv_v6f16(ptr %x, half %y) {
30343031
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
30353032
; ZVFHMIN-NEXT: vle16.v v8, (a0)
30363033
; ZVFHMIN-NEXT: fmv.x.w a1, fa0
3037-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
30383034
; ZVFHMIN-NEXT: vmv.v.x v9, a1
30393035
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
30403036
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
30413037
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
30423038
; ZVFHMIN-NEXT: vfmul.vv v8, v12, v10
3043-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
3039+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
30443040
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
30453041
; ZVFHMIN-NEXT: vse16.v v10, (a0)
30463042
; ZVFHMIN-NEXT: ret
@@ -3176,13 +3172,12 @@ define void @fdiv_vf_v6f16(ptr %x, half %y) {
31763172
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
31773173
; ZVFHMIN-NEXT: vle16.v v8, (a0)
31783174
; ZVFHMIN-NEXT: fmv.x.w a1, fa0
3179-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
31803175
; ZVFHMIN-NEXT: vmv.v.x v9, a1
31813176
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
31823177
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
31833178
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
31843179
; ZVFHMIN-NEXT: vfdiv.vv v8, v10, v12
3185-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
3180+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
31863181
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
31873182
; ZVFHMIN-NEXT: vse16.v v10, (a0)
31883183
; ZVFHMIN-NEXT: ret
@@ -3318,13 +3313,12 @@ define void @fdiv_fv_v6f16(ptr %x, half %y) {
33183313
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
33193314
; ZVFHMIN-NEXT: vle16.v v8, (a0)
33203315
; ZVFHMIN-NEXT: fmv.x.w a1, fa0
3321-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
33223316
; ZVFHMIN-NEXT: vmv.v.x v9, a1
33233317
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
33243318
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
33253319
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
33263320
; ZVFHMIN-NEXT: vfdiv.vv v8, v12, v10
3327-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
3321+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
33283322
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
33293323
; ZVFHMIN-NEXT: vse16.v v10, (a0)
33303324
; ZVFHMIN-NEXT: ret
@@ -4993,12 +4987,11 @@ define void @fmuladd_v6f16(ptr %x, ptr %y, ptr %z) {
49934987
; ZVFHMIN-NEXT: vle16.v v8, (a1)
49944988
; ZVFHMIN-NEXT: vle16.v v9, (a0)
49954989
; ZVFHMIN-NEXT: vle16.v v10, (a2)
4996-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
49974990
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
49984991
; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9
49994992
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
50004993
; ZVFHMIN-NEXT: vfmul.vv v8, v14, v12
5001-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
4994+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
50024995
; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v8
50034996
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11
50044997
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
@@ -5170,12 +5163,11 @@ define void @fmsub_fmuladd_v6f16(ptr %x, ptr %y, ptr %z) {
51705163
; ZVFHMIN-NEXT: vle16.v v8, (a1)
51715164
; ZVFHMIN-NEXT: vle16.v v9, (a0)
51725165
; ZVFHMIN-NEXT: vle16.v v10, (a2)
5173-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
51745166
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
51755167
; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9
51765168
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
51775169
; ZVFHMIN-NEXT: vfmul.vv v8, v14, v12
5178-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
5170+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
51795171
; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v8
51805172
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11
51815173
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3193,3 +3193,103 @@ define <vscale x 4 x double> @vfwsub_wf(<vscale x 4 x double> %a, float %b, iXLe
31933193
%2 = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %1, iXLen 7, iXLen %vl)
31943194
ret <vscale x 4 x double> %2
31953195
}
3196+
3197+
define <vscale x 4 x float> @vfmul_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {
3198+
; NOVLOPT-LABEL: vfmul_vv:
3199+
; NOVLOPT: # %bb.0:
3200+
; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3201+
; NOVLOPT-NEXT: vfmul.vv v8, v8, v10
3202+
; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3203+
; NOVLOPT-NEXT: vfadd.vv v8, v8, v10
3204+
; NOVLOPT-NEXT: ret
3205+
;
3206+
; VLOPT-LABEL: vfmul_vv:
3207+
; VLOPT: # %bb.0:
3208+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3209+
; VLOPT-NEXT: vfmul.vv v8, v8, v10
3210+
; VLOPT-NEXT: vfadd.vv v8, v8, v10
3211+
; VLOPT-NEXT: ret
3212+
%1 = call <vscale x 4 x float> @llvm.riscv.vfmul.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen 7, iXLen -1)
3213+
%2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %b, iXLen 7, iXLen %vl)
3214+
ret <vscale x 4 x float> %2
3215+
}
3216+
3217+
define <vscale x 4 x float> @vfmul_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {
3218+
; NOVLOPT-LABEL: vfmul_vf:
3219+
; NOVLOPT: # %bb.0:
3220+
; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3221+
; NOVLOPT-NEXT: vfmul.vf v10, v8, fa0
3222+
; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3223+
; NOVLOPT-NEXT: vfadd.vv v8, v10, v8
3224+
; NOVLOPT-NEXT: ret
3225+
;
3226+
; VLOPT-LABEL: vfmul_vf:
3227+
; VLOPT: # %bb.0:
3228+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3229+
; VLOPT-NEXT: vfmul.vf v10, v8, fa0
3230+
; VLOPT-NEXT: vfadd.vv v8, v10, v8
3231+
; VLOPT-NEXT: ret
3232+
%1 = call <vscale x 4 x float> @llvm.riscv.vfmul.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen 7, iXLen -1)
3233+
%2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)
3234+
ret <vscale x 4 x float> %2
3235+
}
3236+
3237+
define <vscale x 4 x float> @vfdiv_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {
3238+
; NOVLOPT-LABEL: vfdiv_vv:
3239+
; NOVLOPT: # %bb.0:
3240+
; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3241+
; NOVLOPT-NEXT: vfdiv.vv v8, v8, v10
3242+
; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3243+
; NOVLOPT-NEXT: vfadd.vv v8, v8, v10
3244+
; NOVLOPT-NEXT: ret
3245+
;
3246+
; VLOPT-LABEL: vfdiv_vv:
3247+
; VLOPT: # %bb.0:
3248+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3249+
; VLOPT-NEXT: vfdiv.vv v8, v8, v10
3250+
; VLOPT-NEXT: vfadd.vv v8, v8, v10
3251+
; VLOPT-NEXT: ret
3252+
%1 = call <vscale x 4 x float> @llvm.riscv.vfdiv.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen 7, iXLen -1)
3253+
%2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %b, iXLen 7, iXLen %vl)
3254+
ret <vscale x 4 x float> %2
3255+
}
3256+
3257+
define <vscale x 4 x float> @vfdiv_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {
3258+
; NOVLOPT-LABEL: vfdiv_vf:
3259+
; NOVLOPT: # %bb.0:
3260+
; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3261+
; NOVLOPT-NEXT: vfdiv.vf v10, v8, fa0
3262+
; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3263+
; NOVLOPT-NEXT: vfadd.vv v8, v10, v8
3264+
; NOVLOPT-NEXT: ret
3265+
;
3266+
; VLOPT-LABEL: vfdiv_vf:
3267+
; VLOPT: # %bb.0:
3268+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3269+
; VLOPT-NEXT: vfdiv.vf v10, v8, fa0
3270+
; VLOPT-NEXT: vfadd.vv v8, v10, v8
3271+
; VLOPT-NEXT: ret
3272+
%1 = call <vscale x 4 x float> @llvm.riscv.vfdiv.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen 7, iXLen -1)
3273+
%2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)
3274+
ret <vscale x 4 x float> %2
3275+
}
3276+
3277+
define <vscale x 4 x float> @vfrdiv_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {
3278+
; NOVLOPT-LABEL: vfrdiv_vf:
3279+
; NOVLOPT: # %bb.0:
3280+
; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3281+
; NOVLOPT-NEXT: vfrdiv.vf v10, v8, fa0
3282+
; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3283+
; NOVLOPT-NEXT: vfadd.vv v8, v10, v8
3284+
; NOVLOPT-NEXT: ret
3285+
;
3286+
; VLOPT-LABEL: vfrdiv_vf:
3287+
; VLOPT: # %bb.0:
3288+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3289+
; VLOPT-NEXT: vfrdiv.vf v10, v8, fa0
3290+
; VLOPT-NEXT: vfadd.vv v8, v10, v8
3291+
; VLOPT-NEXT: ret
3292+
%1 = call <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen 7, iXLen -1)
3293+
%2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)
3294+
ret <vscale x 4 x float> %2
3295+
}

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