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AMDGPU: Create InstrMapping from VGPR MFMA to equivalent AGPR instruction
This provides infrastructure for a future optimization.
1 parent 0e3c791 commit a488c17

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3 files changed

+23
-3
lines changed

3 files changed

+23
-3
lines changed

llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1568,6 +1568,11 @@ namespace AMDGPU {
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LLVM_READONLY
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int getMFMAEarlyClobberOp(uint16_t Opcode);
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/// \returns Version of an MFMA instruction which uses AGPRs for srcC and
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/// vdst, given an \p Opcode of an MFMA which uses VGPRs for srcC/vdst.
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LLVM_READONLY
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int getMFMASrcCVDstAGPROp(uint16_t Opcode);
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/// \returns v_cmpx version of a v_cmp instruction.
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LLVM_READONLY
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int getVCMPXOpFromVCMP(uint16_t Opcode);

llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 9 additions & 0 deletions
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@@ -3167,6 +3167,15 @@ def getMFMAEarlyClobberOp : InstrMapping {
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let ValueCols = [["0"]];
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}
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// Map from an mfma using VGPRs to one using AGPRs.
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def getMFMASrcCVDstAGPROp : InstrMapping {
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let FilterClass = "MFMATable";
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let RowFields = ["AGPROp"];
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let ColFields = ["MFMAKind"];
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let KeyCol = ["VGPR"];
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let ValueCols = [["AGPR"]];
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}
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// Maps an v_cmp instruction to its v_cmpx equivalent.
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def getVCMPXOpFromVCMP : InstrMapping {
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let FilterClass = "VCMPVCMPXTable";

llvm/lib/Target/AMDGPU/VOP3PInstructions.td

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -741,9 +741,14 @@ def VOPProfileMAI_I32_V4I32_X16 : VOPProfileMAI<VOP_V16I32_V4I32_V4I32_V16I3
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def VOPProfileMAI_I32_V4I32_X16_VCD : VOPProfileMAI<VOP_V16I32_V4I32_V4I32_V16I32, VISrc_512_b32, VDst_512, AVSrc_128>;
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class MFMATable <bit is_mac, string Name> {
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class MFMATable <bit is_mac, string Kind, string Name,
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string AGPROpName = NAME> {
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bit IsMac = is_mac;
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string FMAOp = Name;
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string AGPROp = AGPROpName;
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// Does this MFMA use "AGPR" or "VGPR" for srcC/vdst
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string MFMAKind = Kind;
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}
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class MFMA_F8F6F4_WithSizeTable<int A, int B, Instruction ThisVariant, Instruction F8F8Variant> {
@@ -849,12 +854,12 @@ multiclass MAIInst<string OpName, string P, SDPatternOperator node = null_frag,
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let Constraints = !if(NoDstOverlap, "@earlyclobber $vdst", "") in {
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def _e64 : MAIInst<OpName, !cast<VOPProfileMAI>("VOPProfileMAI_" # P),
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!if(!or(NoDstOverlap, !eq(node, null_frag)), null_frag, AgprMAIFrag<node, HasAbid, Scaled>), Scaled>,
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MFMATable<0, NAME # "_e64">;
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MFMATable<0, "AGPR", NAME # "_e64">;
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let OtherPredicates = [isGFX90APlus], Mnemonic = OpName in
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def _vgprcd_e64 : MAIInst<OpName # "_vgprcd", !cast<VOPProfileMAI>("VOPProfileMAI_" # P # "_VCD"),
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!if(!or(NoDstOverlap, !eq(node, null_frag)), null_frag, VgprMAIFrag<node, HasAbid, Scaled>), Scaled>,
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MFMATable<0, NAME # "_vgprcd_e64">;
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MFMATable<0, "VGPR", NAME # "_vgprcd_e64", NAME # "_e64">;
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}
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if NoDstOverlap then {
@@ -863,6 +868,7 @@ multiclass MAIInst<string OpName, string P, SDPatternOperator node = null_frag,
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Mnemonic = OpName in {
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def "_mac_e64" : MAIInst<OpName # "_mac", !cast<VOPProfileMAI>("VOPProfileMAI_" # P),
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!if(!eq(node, null_frag), null_frag, AgprMAIFrag<node, HasAbid, Scaled>), Scaled>,
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MFMATable<1, "AGPR", NAME # "_e64", NAME # "_mac_e64">;
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MFMATable<1, NAME # "_e64">;
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let OtherPredicates = [isGFX90APlus] in

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