Skip to content

Commit a527b7c

Browse files
committed
bypass poison check for usub.sat
1 parent 6ba5fd9 commit a527b7c

File tree

2 files changed

+12
-6
lines changed

2 files changed

+12
-6
lines changed

llvm/lib/Transforms/Scalar/ConstraintElimination.cpp

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1132,14 +1132,17 @@ void State::addInfoFor(BasicBlock &BB) {
11321132
case Intrinsic::umax:
11331133
case Intrinsic::smin:
11341134
case Intrinsic::smax:
1135-
case Intrinsic::usub_sat:
11361135
// TODO: handle llvm.abs as well
11371136
WorkList.push_back(
11381137
FactOrCheck::getCheck(DT.getNode(&BB), cast<CallInst>(&I)));
11391138
// TODO: Check if it is possible to instead only added the min/max facts
11401139
// when simplifying uses of the min/max intrinsics.
1141-
if (!isGuaranteedNotToBePoison(&I))
1142-
break;
1140+
if (isGuaranteedNotToBePoison(&I))
1141+
WorkList.push_back(FactOrCheck::getInstFact(DT.getNode(&BB), &I));
1142+
break;
1143+
case Intrinsic::usub_sat:
1144+
WorkList.push_back(
1145+
FactOrCheck::getCheck(DT.getNode(&BB), cast<CallInst>(&I)));
11431146
[[fallthrough]];
11441147
case Intrinsic::abs:
11451148
case Intrinsic::uadd_sat:

llvm/test/Transforms/ConstraintElimination/uadd-usub-sat.ll

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,9 @@ define i1 @uadd_sat_uge(i64 %a, i64 %b) {
88
; CHECK-LABEL: define i1 @uadd_sat_uge(
99
; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
1010
; CHECK-NEXT: [[ADD_SAT:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[A]], i64 [[B]])
11-
; CHECK-NEXT: [[CMP:%.*]] = and i1 true, true
11+
; CHECK-NEXT: [[CMP1:%.*]] = icmp uge i64 [[ADD_SAT]], [[A]]
12+
; CHECK-NEXT: [[CMP2:%.*]] = icmp uge i64 [[ADD_SAT]], [[B]]
13+
; CHECK-NEXT: [[CMP:%.*]] = and i1 [[CMP1]], [[CMP2]]
1214
; CHECK-NEXT: ret i1 [[CMP]]
1315
;
1416
%add.sat = call i64 @llvm.uadd.sat.i64(i64 %a, i64 %b)
@@ -35,7 +37,7 @@ define i64 @usub_sat_when_lhs_ugt_rhs(i64 %a, i64 %b) {
3537
; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
3638
; CHECK-NEXT: [[PRECOND:%.*]] = icmp ugt i64 [[A]], [[B]]
3739
; CHECK-NEXT: call void @llvm.assume(i1 [[PRECOND]])
38-
; CHECK-NEXT: [[SUB_SAT:%.*]] = sub i64 [[A]], [[B]]
40+
; CHECK-NEXT: [[SUB_SAT:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
3941
; CHECK-NEXT: ret i64 [[SUB_SAT]]
4042
;
4143
%precond = icmp ugt i64 %a, %b
@@ -49,7 +51,8 @@ define i64 @usub_sat_when_lhs_ule_rhs(i64 %a, i64 %b) {
4951
; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
5052
; CHECK-NEXT: [[PRECOND:%.*]] = icmp ule i64 [[A]], [[B]]
5153
; CHECK-NEXT: call void @llvm.assume(i1 [[PRECOND]])
52-
; CHECK-NEXT: ret i64 0
54+
; CHECK-NEXT: [[SUB_SAT:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
55+
; CHECK-NEXT: ret i64 [[SUB_SAT]]
5356
;
5457
%precond = icmp ule i64 %a, %b
5558
call void @llvm.assume(i1 %precond)

0 commit comments

Comments
 (0)