@@ -8,7 +8,9 @@ define i1 @uadd_sat_uge(i64 %a, i64 %b) {
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; CHECK-LABEL: define i1 @uadd_sat_uge(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
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; CHECK-NEXT: [[ADD_SAT:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[A]], i64 [[B]])
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- ; CHECK-NEXT: [[CMP:%.*]] = and i1 true, true
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+ ; CHECK-NEXT: [[CMP1:%.*]] = icmp uge i64 [[ADD_SAT]], [[A]]
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+ ; CHECK-NEXT: [[CMP2:%.*]] = icmp uge i64 [[ADD_SAT]], [[B]]
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+ ; CHECK-NEXT: [[CMP:%.*]] = and i1 [[CMP1]], [[CMP2]]
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add.sat = call i64 @llvm.uadd.sat.i64 (i64 %a , i64 %b )
@@ -35,7 +37,7 @@ define i64 @usub_sat_when_lhs_ugt_rhs(i64 %a, i64 %b) {
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
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; CHECK-NEXT: [[PRECOND:%.*]] = icmp ugt i64 [[A]], [[B]]
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; CHECK-NEXT: call void @llvm.assume(i1 [[PRECOND]])
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- ; CHECK-NEXT: [[SUB_SAT:%.*]] = sub i64 [[A]], [[B]]
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+ ; CHECK-NEXT: [[SUB_SAT:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: ret i64 [[SUB_SAT]]
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;
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%precond = icmp ugt i64 %a , %b
@@ -49,7 +51,8 @@ define i64 @usub_sat_when_lhs_ule_rhs(i64 %a, i64 %b) {
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
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; CHECK-NEXT: [[PRECOND:%.*]] = icmp ule i64 [[A]], [[B]]
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; CHECK-NEXT: call void @llvm.assume(i1 [[PRECOND]])
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- ; CHECK-NEXT: ret i64 0
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+ ; CHECK-NEXT: [[SUB_SAT:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
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+ ; CHECK-NEXT: ret i64 [[SUB_SAT]]
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;
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%precond = icmp ule i64 %a , %b
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call void @llvm.assume (i1 %precond )
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