[PHIElimination] Verify COPY has similar register class, update LiveVars

Author: guy-david

llvm/lib/CodeGen/PHIElimination.cpp

@@ -584,9 +584,13 @@ void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
     // Reuse an existing copy in the block if possible.
     if (IncomingReg.isVirtual()) {
       MachineInstr *DefMI = MRI->getUniqueVRegDef(SrcReg);
+      const TargetRegisterClass *RC1 = MRI->getRegClass(SrcReg);
+      const TargetRegisterClass *RC2 = MRI->getRegClass(IncomingReg);
       if (DefMI && DefMI->isCopy() && DefMI->getParent() == &opBlock &&
-          MRI->use_empty(SrcReg)) {
+          MRI->use_empty(SrcReg) && RC2->hasSuperClassEq(RC1)) {
         DefMI->getOperand(0).setReg(IncomingReg);
+        if (LV)
+          LV->getVarInfo(SrcReg).AliveBlocks.clear();
         continue;
       }
     }

llvm/test/CodeGen/AArch64/PHIElimination-reuse-copy.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -run-pass=phi-node-elimination -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
+# RUN: llc -run-pass=livevars,phi-node-elimination -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
 
 # Verify that the original COPY in bb.1 is reappropriated as the PHI source in bb.2,
 # instead of creating a new COPY with the same source register.
@@ -117,3 +117,28 @@ body: |
 
 ...
 
+---
+name:            copy_subreg
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: copy_subreg
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $x0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64 = COPY killed $x0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr64 = COPY killed [[COPY]]
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
+  bb.0:
+    successors: %bb.1
+    liveins: $x0
+
+    %0:gpr64 = COPY killed $x0
+    %1:gpr64 = COPY killed %0
+
+  bb.1:
+    %2:gpr32 = PHI %1.sub_32, %bb.0
+...

llvm/test/CodeGen/AArch64/tbl-loops.ll

@@ -17,18 +17,18 @@ define void @loop1(ptr noalias nocapture noundef writeonly %dst, ptr nocapture n
 ; CHECK-NEXT:  .LBB0_3: // %vector.ph
 ; CHECK-NEXT:    add x11, x8, #1
 ; CHECK-NEXT:    mov w8, #1132396544 // =0x437f0000
-; CHECK-NEXT:    add x13, x0, #4
+; CHECK-NEXT:    add x12, x0, #4
 ; CHECK-NEXT:    and x10, x11, #0x1fffffff8
 ; CHECK-NEXT:    dup v0.4s, w8
-; CHECK-NEXT:    add x14, x1, #16
+; CHECK-NEXT:    add x13, x1, #16
 ; CHECK-NEXT:    add x8, x1, x10, lsl #2
-; CHECK-NEXT:    mov x12, x10
 ; CHECK-NEXT:    add x9, x0, x10
+; CHECK-NEXT:    mov x14, x10
 ; CHECK-NEXT:  .LBB0_4: // %vector.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    ldp q1, q2, [x14, #-16]
-; CHECK-NEXT:    subs x12, x12, #8
-; CHECK-NEXT:    add x14, x14, #32
+; CHECK-NEXT:    ldp q1, q2, [x13, #-16]
+; CHECK-NEXT:    subs x14, x14, #8
+; CHECK-NEXT:    add x13, x13, #32
 ; CHECK-NEXT:    fcmgt v3.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    fcmgt v4.4s, v2.4s, v0.4s
 ; CHECK-NEXT:    fcmlt v5.4s, v1.4s, #0.0
@@ -44,8 +44,8 @@ define void @loop1(ptr noalias nocapture noundef writeonly %dst, ptr nocapture n
 ; CHECK-NEXT:    uzp1 v1.8b, v1.8b, v0.8b
 ; CHECK-NEXT:    uzp1 v2.8b, v2.8b, v0.8b
 ; CHECK-NEXT:    mov v1.s[1], v2.s[0]
-; CHECK-NEXT:    stur d1, [x13, #-4]
-; CHECK-NEXT:    add x13, x13, #8
+; CHECK-NEXT:    stur d1, [x12, #-4]
+; CHECK-NEXT:    add x12, x12, #8
 ; CHECK-NEXT:    b.ne .LBB0_4
 ; CHECK-NEXT:  // %bb.5: // %middle.block
 ; CHECK-NEXT:    cmp x11, x10