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[Hexagon] Add V75 support to compiler and assembler
This patch introduces support for the Hexagon V75 architecture. It includes instruction formats, definitions, encodings, scheduling classes, and builtins/intrinsics.
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21 files changed

+1656
-36
lines changed

21 files changed

+1656
-36
lines changed

‎clang/include/clang/Basic/BuiltinsHexagon.def

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,10 @@
1717
# define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
1818
#endif
1919

20+
#pragma push_macro("V75")
21+
#define V75 "v75"
2022
#pragma push_macro("V73")
21-
#define V73 "v73"
23+
#define V73 "v73|" V75
2224
#pragma push_macro("V71")
2325
#define V71 "v71|" V73
2426
#pragma push_macro("V69")
@@ -40,8 +42,10 @@
4042
#pragma push_macro("V5")
4143
#define V5 "v5|" V55
4244

45+
#pragma push_macro("HVXV75")
46+
#define HVXV75 "hvxv75"
4347
#pragma push_macro("HVXV73")
44-
#define HVXV73 "hvxv73"
48+
#define HVXV73 "hvxv73|" HVXV75
4549
#pragma push_macro("HVXV71")
4650
#define HVXV71 "hvxv71|" HVXV73
4751
#pragma push_macro("HVXV69")
@@ -143,6 +147,7 @@ TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
143147
#pragma pop_macro("HVXV69")
144148
#pragma pop_macro("HVXV71")
145149
#pragma pop_macro("HVXV73")
150+
#pragma pop_macro("HVXV75")
146151

147152
#pragma pop_macro("V5")
148153
#pragma pop_macro("V55")
@@ -155,6 +160,7 @@ TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
155160
#pragma pop_macro("V69")
156161
#pragma pop_macro("V71")
157162
#pragma pop_macro("V73")
163+
#pragma pop_macro("V75")
158164

159165
#undef BUILTIN
160166
#undef TARGET_BUILTIN

‎clang/include/clang/Driver/Options.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6224,6 +6224,8 @@ def mv71t : Flag<["-"], "mv71t">, Group<m_hexagon_Features_Group>,
62246224
Alias<mcpu_EQ>, AliasArgs<["hexagonv71t"]>;
62256225
def mv73 : Flag<["-"], "mv73">, Group<m_hexagon_Features_Group>,
62266226
Alias<mcpu_EQ>, AliasArgs<["hexagonv73"]>;
6227+
def mv75 : Flag<["-"], "mv75">, Group<m_hexagon_Features_Group>,
6228+
Alias<mcpu_EQ>, AliasArgs<["hexagonv75"]>;
62276229
def mhexagon_hvx : Flag<["-"], "mhvx">, Group<m_hexagon_Features_HVX_Group>,
62286230
HelpText<"Enable Hexagon Vector eXtensions">;
62296231
def mhexagon_hvx_EQ : Joined<["-"], "mhvx=">,

‎clang/lib/Basic/Targets/Hexagon.cpp

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,9 @@ void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
7878
} else if (CPU == "hexagonv73") {
7979
Builder.defineMacro("__HEXAGON_V73__");
8080
Builder.defineMacro("__HEXAGON_ARCH__", "73");
81+
} else if (CPU == "hexagonv75") {
82+
Builder.defineMacro("__HEXAGON_V75__");
83+
Builder.defineMacro("__HEXAGON_ARCH__", "75");
8184
}
8285

8386
if (hasFeature("hvx-length64b")) {
@@ -229,13 +232,13 @@ struct CPUSuffix {
229232
};
230233

231234
static constexpr CPUSuffix Suffixes[] = {
232-
{{"hexagonv5"}, {"5"}}, {{"hexagonv55"}, {"55"}},
233-
{{"hexagonv60"}, {"60"}}, {{"hexagonv62"}, {"62"}},
234-
{{"hexagonv65"}, {"65"}}, {{"hexagonv66"}, {"66"}},
235+
{{"hexagonv5"}, {"5"}}, {{"hexagonv55"}, {"55"}},
236+
{{"hexagonv60"}, {"60"}}, {{"hexagonv62"}, {"62"}},
237+
{{"hexagonv65"}, {"65"}}, {{"hexagonv66"}, {"66"}},
235238
{{"hexagonv67"}, {"67"}}, {{"hexagonv67t"}, {"67t"}},
236-
{{"hexagonv68"}, {"68"}}, {{"hexagonv69"}, {"69"}},
237-
{{"hexagonv71"}, {"71"}}, {{"hexagonv71t"}, {"71t"}},
238-
{{"hexagonv73"}, {"73"}},
239+
{{"hexagonv68"}, {"68"}}, {{"hexagonv69"}, {"69"}},
240+
{{"hexagonv71"}, {"71"}}, {{"hexagonv71t"}, {"71t"}},
241+
{{"hexagonv73"}, {"73"}}, {{"hexagonv75"}, {"75"}},
239242
};
240243

241244
std::optional<unsigned> HexagonTargetInfo::getHexagonCPURev(StringRef Name) {

‎clang/test/Driver/hexagon-toolchain-elf.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -152,6 +152,13 @@
152152
// CHECK230: "-cc1" {{.*}} "-target-cpu" "hexagonv73"
153153
// CHECK230: hexagon-link{{.*}}/Inputs/hexagon_tree/Tools/bin/../target/hexagon/lib/v73/crt0
154154

155+
// RUN: not %clang -### --target=hexagon-unknown-elf \
156+
// RUN: -ccc-install-dir %S/Inputs/hexagon_tree/Tools/bin \
157+
// RUN: -mcpu=hexagonv75 -fuse-ld=hexagon-link \
158+
// RUN: %s 2>&1 | FileCheck -check-prefix=CHECK240 %s
159+
// CHECK240: "-cc1" {{.*}} "-target-cpu" "hexagonv75"
160+
// CHECK240: hexagon-link{{.*}}/Inputs/hexagon_tree/Tools/bin/../target/hexagon/lib/v75/crt0
161+
155162
// -----------------------------------------------------------------------------
156163
// Test Linker related args
157164
// -----------------------------------------------------------------------------

‎clang/test/Misc/target-invalid-cpu-note/hexagon.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,4 +18,5 @@
1818
// CHECK-SAME: {{^}}, hexagonv71
1919
// CHECK-SAME: {{^}}, hexagonv71t
2020
// CHECK-SAME: {{^}}, hexagonv73
21+
// CHECK-SAME: {{^}}, hexagonv75
2122
// CHECK-SAME: {{$}}

‎clang/test/Preprocessor/hexagon-predefines.c

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -137,6 +137,22 @@
137137
// CHECK-V73HVX-128B: #define __HVX__ 1
138138
// CHECK-V73HVX-128B: #define __hexagon__ 1
139139

140+
// RUN: %clang_cc1 -E -dM -triple hexagon-unknown-elf -target-cpu hexagonv75 %s\
141+
// RUN: | FileCheck %s -check-prefix CHECK-V75
142+
// CHECK-V75: #define __HEXAGON_ARCH__ 75
143+
// CHECK-V75: #define __HEXAGON_PHYSICAL_SLOTS__ 4
144+
// CHECK-V75: #define __HEXAGON_V75__ 1
145+
// CHECK-V75: #define __hexagon__ 1
146+
147+
// RUN: %clang_cc1 -E -dM -triple hexagon-unknown-elf -target-cpu hexagonv75 \
148+
// RUN: -target-feature +hvxv75 -target-feature +hvx-length128b %s | FileCheck \
149+
// RUN: %s -check-prefix CHECK-V75HVX-128B
150+
// CHECK-V75HVX-128B: #define __HEXAGON_ARCH__ 75
151+
// CHECK-V75HVX-128B: #define __HEXAGON_V75__ 1
152+
// CHECK-V75HVX-128B: #define __HVX_ARCH__ 75
153+
// CHECK-V75HVX-128B: #define __HVX_LENGTH__ 128
154+
// CHECK-V75HVX-128B: #define __HVX__ 1
155+
// CHECK-V75HVX-128B: #define __hexagon__ 1
140156

141157
// RUN: %clang_cc1 -E -dM -triple hexagon-unknown-elf -target-cpu hexagonv67 \
142158
// RUN: -target-feature +hvxv67 -target-feature +hvx-length128b %s | FileCheck \

‎llvm/include/llvm/BinaryFormat/ELF.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -629,6 +629,7 @@ enum {
629629
EF_HEXAGON_MACH_V71 = 0x00000071, // Hexagon V71
630630
EF_HEXAGON_MACH_V71T = 0x00008071, // Hexagon V71T
631631
EF_HEXAGON_MACH_V73 = 0x00000073, // Hexagon V73
632+
EF_HEXAGON_MACH_V75 = 0x00000075, // Hexagon V75
632633
EF_HEXAGON_MACH = 0x000003ff, // Hexagon V..
633634

634635
// Highest ISA version flags

‎llvm/lib/Object/ELFObjectFile.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -309,6 +309,8 @@ static std::optional<std::string> hexagonAttrToFeatureString(unsigned Attr) {
309309
return "v71";
310310
case 73:
311311
return "v73";
312+
case 75:
313+
return "v75";
312314
default:
313315
return {};
314316
}

‎llvm/lib/ObjectYAML/ELFYAML.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -496,6 +496,7 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
496496
BCaseMask(EF_HEXAGON_MACH_V71, EF_HEXAGON_MACH);
497497
BCaseMask(EF_HEXAGON_MACH_V71T, EF_HEXAGON_MACH);
498498
BCaseMask(EF_HEXAGON_MACH_V73, EF_HEXAGON_MACH);
499+
BCaseMask(EF_HEXAGON_MACH_V75, EF_HEXAGON_MACH);
499500
BCaseMask(EF_HEXAGON_ISA_V2, EF_HEXAGON_ISA);
500501
BCaseMask(EF_HEXAGON_ISA_V3, EF_HEXAGON_ISA);
501502
BCaseMask(EF_HEXAGON_ISA_V4, EF_HEXAGON_ISA);
@@ -510,6 +511,7 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
510511
BCaseMask(EF_HEXAGON_ISA_V69, EF_HEXAGON_ISA);
511512
BCaseMask(EF_HEXAGON_ISA_V71, EF_HEXAGON_ISA);
512513
BCaseMask(EF_HEXAGON_ISA_V73, EF_HEXAGON_ISA);
514+
BCaseMask(EF_HEXAGON_ISA_V75, EF_HEXAGON_ISA);
513515
break;
514516
case ELF::EM_AVR:
515517
BCaseMask(EF_AVR_ARCH_AVR1, EF_AVR_ARCH_MASK);

‎llvm/lib/Target/Hexagon/Hexagon.td

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,12 @@ def ExtensionHVXV73: SubtargetFeature<"hvxv73", "HexagonHVXVersion",
6767
[ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
6868
ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71]>;
6969

70+
def ExtensionHVXV75: SubtargetFeature<"hvxv75", "HexagonHVXVersion",
71+
"Hexagon::ArchEnum::V75", "Hexagon HVX instructions",
72+
[ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
73+
ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,
74+
ExtensionHVXV73]>;
75+
7076
def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
7177
"true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
7278
def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",
@@ -137,6 +143,8 @@ def UseHVXV71 : Predicate<"HST->useHVXV71Ops()">,
137143
AssemblerPredicate<(all_of ExtensionHVXV71)>;
138144
def UseHVXV73 : Predicate<"HST->useHVXV73Ops()">,
139145
AssemblerPredicate<(all_of ExtensionHVXV73)>;
146+
def UseHVXV75 : Predicate<"HST->useHVXV75Ops()">,
147+
AssemblerPredicate<(all_of ExtensionHVXV75)>;
140148
def UseAudio : Predicate<"HST->useAudioOps()">,
141149
AssemblerPredicate<(all_of ExtensionAudio)>;
142150
def UseZReg : Predicate<"HST->useZRegOps()">,
@@ -462,6 +470,12 @@ def : Proc<"hexagonv73", HexagonModelV73,
462470
ArchV68, ArchV69, ArchV71, ArchV73,
463471
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
464472
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
473+
def : Proc<"hexagonv75", HexagonModelV75,
474+
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
475+
ArchV68, ArchV69, ArchV71, ArchV73, ArchV75, FeatureCompound,
476+
FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
477+
FeatureNVS, FeaturePackets, FeatureSmallData]>;
478+
465479
// Need to update the correct features for tiny core.
466480
// Disable NewValueJumps since the packetizer is unable to handle a packet with
467481
// a new value jump and another SLOT0 instruction.

‎llvm/lib/Target/Hexagon/HexagonDepArch.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,8 @@ enum class ArchEnum {
2727
V68,
2828
V69,
2929
V71,
30-
V73
30+
V73,
31+
V75
3132
};
3233

3334
inline std::optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
@@ -46,6 +47,7 @@ inline std::optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
4647
.Case("hexagonv71", Hexagon::ArchEnum::V71)
4748
.Case("hexagonv71t", Hexagon::ArchEnum::V71)
4849
.Case("hexagonv73", Hexagon::ArchEnum::V73)
50+
.Case("hexagonv75", Hexagon::ArchEnum::V75)
4951
.Default(std::nullopt);
5052
}
5153
} // namespace Hexagon

‎llvm/lib/Target/Hexagon/HexagonDepArch.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,3 +30,5 @@ def ArchV71: SubtargetFeature<"v71", "HexagonArchVersion", "Hexagon::ArchEnum::V
3030
def HasV71 : Predicate<"HST->hasV71Ops()">, AssemblerPredicate<(all_of ArchV71)>;
3131
def ArchV73: SubtargetFeature<"v73", "HexagonArchVersion", "Hexagon::ArchEnum::V73", "Enable Hexagon V73 architecture">;
3232
def HasV73 : Predicate<"HST->hasV73Ops()">, AssemblerPredicate<(all_of ArchV73)>;
33+
def ArchV75: SubtargetFeature<"v75", "HexagonArchVersion", "Hexagon::ArchEnum::V75", "Enable Hexagon V75 architecture">;
34+
def HasV75 : Predicate<"HST->hasV75Ops()">, AssemblerPredicate<(all_of ArchV75)>;

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