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[RISCV] Support fmaximum/fminimum for fp16 vector when only Zvfhmin enabled
This patch promotes fmaximum/fminimum for fp16 vector to float operation.
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5 files changed

+1036
-327
lines changed

5 files changed

+1036
-327
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -826,7 +826,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
826826
ISD::FMUL, ISD::FMA, ISD::FDIV, ISD::FSQRT,
827827
ISD::FABS, ISD::FNEG, ISD::FCOPYSIGN, ISD::FCEIL,
828828
ISD::FFLOOR, ISD::FROUND, ISD::FROUNDEVEN, ISD::FRINT,
829-
ISD::FNEARBYINT, ISD::IS_FPCLASS, ISD::SPLAT_VECTOR, ISD::SETCC};
829+
ISD::FNEARBYINT, ISD::IS_FPCLASS, ISD::SPLAT_VECTOR, ISD::SETCC,
830+
ISD::FMAXIMUM, ISD::FMINIMUM};
830831

831832
// TODO: support more vp ops.
832833
static const unsigned ZvfhminPromoteVPOps[] = {
@@ -5659,6 +5660,10 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
56595660
}
56605661
case ISD::FMAXIMUM:
56615662
case ISD::FMINIMUM:
5663+
if (Op.getValueType() == MVT::nxv32f16 &&
5664+
(Subtarget.hasVInstructionsF16Minimal() &&
5665+
!Subtarget.hasVInstructionsF16()))
5666+
return SplitVectorOp(Op, DAG);
56625667
return lowerFMAXIMUM_FMINIMUM(Op, DAG, Subtarget);
56635668
case ISD::FP_EXTEND: {
56645669
SDLoc DL(Op);

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll

Lines changed: 194 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -1,73 +1,141 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
3-
; RUN: -verify-machineinstrs < %s | FileCheck %s
3+
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
44
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
5-
; RUN: -verify-machineinstrs < %s | FileCheck %s
5+
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
6+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \
7+
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
8+
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \
9+
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
610

711
declare <2 x half> @llvm.maximum.v2f16(<2 x half>, <2 x half>)
812

913
define <2 x half> @vfmax_v2f16_vv(<2 x half> %a, <2 x half> %b) {
10-
; CHECK-LABEL: vfmax_v2f16_vv:
11-
; CHECK: # %bb.0:
12-
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
13-
; CHECK-NEXT: vmfeq.vv v0, v8, v8
14-
; CHECK-NEXT: vmfeq.vv v10, v9, v9
15-
; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
16-
; CHECK-NEXT: vmv1r.v v0, v10
17-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
18-
; CHECK-NEXT: vfmax.vv v8, v8, v11
19-
; CHECK-NEXT: ret
14+
; ZVFH-LABEL: vfmax_v2f16_vv:
15+
; ZVFH: # %bb.0:
16+
; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
17+
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
18+
; ZVFH-NEXT: vmfeq.vv v10, v9, v9
19+
; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
20+
; ZVFH-NEXT: vmv1r.v v0, v10
21+
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
22+
; ZVFH-NEXT: vfmax.vv v8, v8, v11
23+
; ZVFH-NEXT: ret
24+
;
25+
; ZVFHMIN-LABEL: vfmax_v2f16_vv:
26+
; ZVFHMIN: # %bb.0:
27+
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
28+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
29+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
30+
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
31+
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
32+
; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10
33+
; ZVFHMIN-NEXT: vmerge.vvm v11, v9, v10, v0
34+
; ZVFHMIN-NEXT: vmv1r.v v0, v8
35+
; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v9, v0
36+
; ZVFHMIN-NEXT: vfmax.vv v9, v8, v11
37+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
38+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
39+
; ZVFHMIN-NEXT: ret
2040
%v = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b)
2141
ret <2 x half> %v
2242
}
2343

2444
declare <4 x half> @llvm.maximum.v4f16(<4 x half>, <4 x half>)
2545

2646
define <4 x half> @vfmax_v4f16_vv(<4 x half> %a, <4 x half> %b) {
27-
; CHECK-LABEL: vfmax_v4f16_vv:
28-
; CHECK: # %bb.0:
29-
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
30-
; CHECK-NEXT: vmfeq.vv v0, v8, v8
31-
; CHECK-NEXT: vmfeq.vv v10, v9, v9
32-
; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
33-
; CHECK-NEXT: vmv1r.v v0, v10
34-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
35-
; CHECK-NEXT: vfmax.vv v8, v8, v11
36-
; CHECK-NEXT: ret
47+
; ZVFH-LABEL: vfmax_v4f16_vv:
48+
; ZVFH: # %bb.0:
49+
; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
50+
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
51+
; ZVFH-NEXT: vmfeq.vv v10, v9, v9
52+
; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
53+
; ZVFH-NEXT: vmv1r.v v0, v10
54+
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
55+
; ZVFH-NEXT: vfmax.vv v8, v8, v11
56+
; ZVFH-NEXT: ret
57+
;
58+
; ZVFHMIN-LABEL: vfmax_v4f16_vv:
59+
; ZVFHMIN: # %bb.0:
60+
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
61+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
62+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
63+
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
64+
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
65+
; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10
66+
; ZVFHMIN-NEXT: vmerge.vvm v11, v9, v10, v0
67+
; ZVFHMIN-NEXT: vmv.v.v v0, v8
68+
; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v9, v0
69+
; ZVFHMIN-NEXT: vfmax.vv v9, v8, v11
70+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
71+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
72+
; ZVFHMIN-NEXT: ret
3773
%v = call <4 x half> @llvm.maximum.v4f16(<4 x half> %a, <4 x half> %b)
3874
ret <4 x half> %v
3975
}
4076

4177
declare <8 x half> @llvm.maximum.v8f16(<8 x half>, <8 x half>)
4278

4379
define <8 x half> @vfmax_v8f16_vv(<8 x half> %a, <8 x half> %b) {
44-
; CHECK-LABEL: vfmax_v8f16_vv:
45-
; CHECK: # %bb.0:
46-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
47-
; CHECK-NEXT: vmfeq.vv v0, v8, v8
48-
; CHECK-NEXT: vmfeq.vv v10, v9, v9
49-
; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
50-
; CHECK-NEXT: vmv.v.v v0, v10
51-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
52-
; CHECK-NEXT: vfmax.vv v8, v8, v11
53-
; CHECK-NEXT: ret
80+
; ZVFH-LABEL: vfmax_v8f16_vv:
81+
; ZVFH: # %bb.0:
82+
; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
83+
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
84+
; ZVFH-NEXT: vmfeq.vv v10, v9, v9
85+
; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
86+
; ZVFH-NEXT: vmv.v.v v0, v10
87+
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
88+
; ZVFH-NEXT: vfmax.vv v8, v8, v11
89+
; ZVFH-NEXT: ret
90+
;
91+
; ZVFHMIN-LABEL: vfmax_v8f16_vv:
92+
; ZVFHMIN: # %bb.0:
93+
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
94+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
95+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
96+
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
97+
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
98+
; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10
99+
; ZVFHMIN-NEXT: vmerge.vvm v14, v12, v10, v0
100+
; ZVFHMIN-NEXT: vmv1r.v v0, v8
101+
; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
102+
; ZVFHMIN-NEXT: vfmax.vv v10, v8, v14
103+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
104+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
105+
; ZVFHMIN-NEXT: ret
54106
%v = call <8 x half> @llvm.maximum.v8f16(<8 x half> %a, <8 x half> %b)
55107
ret <8 x half> %v
56108
}
57109

58110
declare <16 x half> @llvm.maximum.v16f16(<16 x half>, <16 x half>)
59111

60112
define <16 x half> @vfmax_v16f16_vv(<16 x half> %a, <16 x half> %b) {
61-
; CHECK-LABEL: vfmax_v16f16_vv:
62-
; CHECK: # %bb.0:
63-
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
64-
; CHECK-NEXT: vmfeq.vv v0, v8, v8
65-
; CHECK-NEXT: vmfeq.vv v12, v10, v10
66-
; CHECK-NEXT: vmerge.vvm v14, v8, v10, v0
67-
; CHECK-NEXT: vmv1r.v v0, v12
68-
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
69-
; CHECK-NEXT: vfmax.vv v8, v8, v14
70-
; CHECK-NEXT: ret
113+
; ZVFH-LABEL: vfmax_v16f16_vv:
114+
; ZVFH: # %bb.0:
115+
; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
116+
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
117+
; ZVFH-NEXT: vmfeq.vv v12, v10, v10
118+
; ZVFH-NEXT: vmerge.vvm v14, v8, v10, v0
119+
; ZVFH-NEXT: vmv1r.v v0, v12
120+
; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
121+
; ZVFH-NEXT: vfmax.vv v8, v8, v14
122+
; ZVFH-NEXT: ret
123+
;
124+
; ZVFHMIN-LABEL: vfmax_v16f16_vv:
125+
; ZVFHMIN: # %bb.0:
126+
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
127+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
128+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
129+
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
130+
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
131+
; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12
132+
; ZVFHMIN-NEXT: vmerge.vvm v20, v16, v12, v0
133+
; ZVFHMIN-NEXT: vmv1r.v v0, v8
134+
; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
135+
; ZVFHMIN-NEXT: vfmax.vv v12, v8, v20
136+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
137+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
138+
; ZVFHMIN-NEXT: ret
71139
%v = call <16 x half> @llvm.maximum.v16f16(<16 x half> %a, <16 x half> %b)
72140
ret <16 x half> %v
73141
}
@@ -220,46 +288,103 @@ define <16 x double> @vfmax_v16f64_vv(<16 x double> %a, <16 x double> %b) nounwi
220288
}
221289

222290
define <2 x half> @vfmax_v2f16_vv_nnan(<2 x half> %a, <2 x half> %b) {
223-
; CHECK-LABEL: vfmax_v2f16_vv_nnan:
224-
; CHECK: # %bb.0:
225-
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
226-
; CHECK-NEXT: vfmax.vv v8, v8, v9
227-
; CHECK-NEXT: ret
291+
; ZVFH-LABEL: vfmax_v2f16_vv_nnan:
292+
; ZVFH: # %bb.0:
293+
; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
294+
; ZVFH-NEXT: vfmax.vv v8, v8, v9
295+
; ZVFH-NEXT: ret
296+
;
297+
; ZVFHMIN-LABEL: vfmax_v2f16_vv_nnan:
298+
; ZVFHMIN: # %bb.0:
299+
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
300+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
301+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
302+
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
303+
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10
304+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
305+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
306+
; ZVFHMIN-NEXT: ret
228307
%v = call nnan <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b)
229308
ret <2 x half> %v
230309
}
231310

232311
; FIXME: The nnan from fadd isn't propagating.
233312
define <2 x half> @vfmax_v2f16_vv_nnana(<2 x half> %a, <2 x half> %b) {
234-
; CHECK-LABEL: vfmax_v2f16_vv_nnana:
235-
; CHECK: # %bb.0:
236-
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
237-
; CHECK-NEXT: vfadd.vv v10, v8, v8
238-
; CHECK-NEXT: vmfeq.vv v0, v9, v9
239-
; CHECK-NEXT: vmfeq.vv v8, v10, v10
240-
; CHECK-NEXT: vmerge.vvm v11, v9, v10, v0
241-
; CHECK-NEXT: vmv1r.v v0, v8
242-
; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0
243-
; CHECK-NEXT: vfmax.vv v8, v11, v8
244-
; CHECK-NEXT: ret
313+
; ZVFH-LABEL: vfmax_v2f16_vv_nnana:
314+
; ZVFH: # %bb.0:
315+
; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
316+
; ZVFH-NEXT: vfadd.vv v10, v8, v8
317+
; ZVFH-NEXT: vmfeq.vv v0, v9, v9
318+
; ZVFH-NEXT: vmfeq.vv v8, v10, v10
319+
; ZVFH-NEXT: vmerge.vvm v11, v9, v10, v0
320+
; ZVFH-NEXT: vmv1r.v v0, v8
321+
; ZVFH-NEXT: vmerge.vvm v8, v10, v9, v0
322+
; ZVFH-NEXT: vfmax.vv v8, v11, v8
323+
; ZVFH-NEXT: ret
324+
;
325+
; ZVFHMIN-LABEL: vfmax_v2f16_vv_nnana:
326+
; ZVFHMIN: # %bb.0:
327+
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
328+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
329+
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
330+
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10
331+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
332+
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
333+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9
334+
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
335+
; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11
336+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
337+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
338+
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
339+
; ZVFHMIN-NEXT: vmfeq.vv v8, v9, v9
340+
; ZVFHMIN-NEXT: vmerge.vvm v10, v11, v9, v0
341+
; ZVFHMIN-NEXT: vmv1r.v v0, v8
342+
; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v0
343+
; ZVFHMIN-NEXT: vfmax.vv v9, v10, v8
344+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
345+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
346+
; ZVFHMIN-NEXT: ret
245347
%c = fadd nnan <2 x half> %a, %a
246348
%v = call <2 x half> @llvm.maximum.v2f16(<2 x half> %c, <2 x half> %b)
247349
ret <2 x half> %v
248350
}
249351

250352
; FIXME: The nnan from fadd isn't propagating.
251353
define <2 x half> @vfmax_v2f16_vv_nnanb(<2 x half> %a, <2 x half> %b) {
252-
; CHECK-LABEL: vfmax_v2f16_vv_nnanb:
253-
; CHECK: # %bb.0:
254-
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
255-
; CHECK-NEXT: vfadd.vv v10, v9, v9
256-
; CHECK-NEXT: vmfeq.vv v0, v8, v8
257-
; CHECK-NEXT: vmfeq.vv v9, v10, v10
258-
; CHECK-NEXT: vmerge.vvm v11, v8, v10, v0
259-
; CHECK-NEXT: vmv1r.v v0, v9
260-
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
261-
; CHECK-NEXT: vfmax.vv v8, v8, v11
262-
; CHECK-NEXT: ret
354+
; ZVFH-LABEL: vfmax_v2f16_vv_nnanb:
355+
; ZVFH: # %bb.0:
356+
; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
357+
; ZVFH-NEXT: vfadd.vv v10, v9, v9
358+
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
359+
; ZVFH-NEXT: vmfeq.vv v9, v10, v10
360+
; ZVFH-NEXT: vmerge.vvm v11, v8, v10, v0
361+
; ZVFH-NEXT: vmv1r.v v0, v9
362+
; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
363+
; ZVFH-NEXT: vfmax.vv v8, v8, v11
364+
; ZVFH-NEXT: ret
365+
;
366+
; ZVFHMIN-LABEL: vfmax_v2f16_vv_nnanb:
367+
; ZVFHMIN: # %bb.0:
368+
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
369+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
370+
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
371+
; ZVFHMIN-NEXT: vfadd.vv v9, v10, v10
372+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
373+
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
374+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
375+
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
376+
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
377+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
378+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v10
379+
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
380+
; ZVFHMIN-NEXT: vmfeq.vv v8, v11, v11
381+
; ZVFHMIN-NEXT: vmerge.vvm v10, v9, v11, v0
382+
; ZVFHMIN-NEXT: vmv1r.v v0, v8
383+
; ZVFHMIN-NEXT: vmerge.vvm v8, v11, v9, v0
384+
; ZVFHMIN-NEXT: vfmax.vv v9, v8, v10
385+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
386+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
387+
; ZVFHMIN-NEXT: ret
263388
%c = fadd nnan <2 x half> %b, %b
264389
%v = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %c)
265390
ret <2 x half> %v

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