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sjoerdmeijersjoerdmeijer
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[AArch64] Fix schedmodel pre/post-index loads and stores for Neoverse V2
Fix the operand description: the update was in the wrong place. As a result the latency of the update was modelled incorrectly, it wasn't available as early as it should. This was visible in llvm-mca timeline views. This fixes the problem for the Neoverse V2, but the problem also affects the other Neoverse cores. Patch by: Ricardo Jesus Differential Revision: https://reviews.llvm.org/D159254
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‎llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td

Lines changed: 53 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -1213,7 +1213,7 @@ def : InstRW<[V2Write_5cyc_1L_1F], (instrs LDRWl, LDRXl, LDRSWl, PRFMl)>;
12131213
def : InstRW<[V2Write_5cyc_1I_3L, WriteLDHi], (instrs LDPSWi)>;
12141214

12151215
// Load pair, immed post-index or immed pre-index, signed words
1216-
def : InstRW<[V2Write_5cyc_1I_3L, WriteLDHi, WriteAdr],
1216+
def : InstRW<[WriteAdr, V2Write_5cyc_1I_3L, WriteLDHi],
12171217
(instregex "^LDPSW(post|pre)$")>;
12181218

12191219
// Store instructions
@@ -1224,7 +1224,7 @@ def : InstRW<[V2Write_5cyc_1I_3L, WriteLDHi, WriteAdr],
12241224
def : SchedAlias<WriteST, V2Write_1cyc_1L01_1D>;
12251225
def : SchedAlias<WriteSTIdx, V2Write_1cyc_1L01_1D>;
12261226
def : SchedAlias<WriteSTP, V2Write_1cyc_1L01_1D>;
1227-
def : SchedAlias<WriteAdr, V2Write_1cyc_1I>; // copied from A57.
1227+
def : SchedAlias<WriteAdr, V2Write_1cyc_1I>;
12281228

12291229
// Tag load instructions
12301230
// -----------------------------------------------------------------------------
@@ -1337,7 +1337,7 @@ def : InstRW<[V2Write_6cyc_1L], (instregex "^LDUR[BHSDQ]i$")>;
13371337

13381338
// Load vector reg, immed post-index
13391339
// Load vector reg, immed pre-index
1340-
def : InstRW<[V2Write_6cyc_1I_1L, WriteAdr],
1340+
def : InstRW<[WriteAdr, V2Write_6cyc_1I_1L],
13411341
(instregex "^LDR[BHSDQ](pre|post)$")>;
13421342

13431343
// Load vector reg, unsigned immed
@@ -1359,12 +1359,12 @@ def : InstRW<[V2Write_6cyc_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>;
13591359

13601360
// Load vector pair, immed post-index, S/D-form
13611361
// Load vector pair, immed pre-index, S/D-form
1362-
def : InstRW<[V2Write_6cyc_1I_1L, WriteLDHi, WriteAdr],
1362+
def : InstRW<[WriteAdr, V2Write_6cyc_1I_1L, WriteLDHi],
13631363
(instregex "^LDP[SD](pre|post)$")>;
13641364

13651365
// Load vector pair, immed post-index, Q-form
13661366
// Load vector pair, immed pre-index, Q-form
1367-
def : InstRW<[V2Write_6cyc_2I_2L, WriteLDHi, WriteAdr], (instrs LDPQpost,
1367+
def : InstRW<[WriteAdr, V2Write_6cyc_2I_2L, WriteLDHi], (instrs LDPQpost,
13681368
LDPQpre)>;
13691369

13701370
// FP store instructions
@@ -1725,220 +1725,220 @@ def : InstRW<[V2Write_5cyc_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;
17251725

17261726
// ASIMD load, 1 element, multiple, 1 reg, D-form
17271727
def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>;
1728-
def : InstRW<[V2Write_6cyc_1L, WriteAdr],
1728+
def : InstRW<[WriteAdr, V2Write_6cyc_1L],
17291729
(instregex "^LD1Onev(8b|4h|2s|1d)_POST$")>;
17301730

17311731
// ASIMD load, 1 element, multiple, 1 reg, Q-form
17321732
def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>;
1733-
def : InstRW<[V2Write_6cyc_1L, WriteAdr],
1733+
def : InstRW<[WriteAdr, V2Write_6cyc_1L],
17341734
(instregex "^LD1Onev(16b|8h|4s|2d)_POST$")>;
17351735

17361736
// ASIMD load, 1 element, multiple, 2 reg, D-form
17371737
def : InstRW<[V2Write_6cyc_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>;
1738-
def : InstRW<[V2Write_6cyc_2L, WriteAdr],
1738+
def : InstRW<[WriteAdr, V2Write_6cyc_2L],
17391739
(instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>;
17401740

17411741
// ASIMD load, 1 element, multiple, 2 reg, Q-form
17421742
def : InstRW<[V2Write_6cyc_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>;
1743-
def : InstRW<[V2Write_6cyc_2L, WriteAdr],
1743+
def : InstRW<[WriteAdr, V2Write_6cyc_2L],
17441744
(instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>;
17451745

17461746
// ASIMD load, 1 element, multiple, 3 reg, D-form
17471747
def : InstRW<[V2Write_6cyc_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>;
1748-
def : InstRW<[V2Write_6cyc_3L, WriteAdr],
1748+
def : InstRW<[WriteAdr, V2Write_6cyc_3L],
17491749
(instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>;
17501750

17511751
// ASIMD load, 1 element, multiple, 3 reg, Q-form
17521752
def : InstRW<[V2Write_6cyc_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>;
1753-
def : InstRW<[V2Write_6cyc_3L, WriteAdr],
1753+
def : InstRW<[WriteAdr, V2Write_6cyc_3L],
17541754
(instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>;
17551755

17561756
// ASIMD load, 1 element, multiple, 4 reg, D-form
17571757
def : InstRW<[V2Write_7cyc_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;
1758-
def : InstRW<[V2Write_7cyc_4L, WriteAdr],
1758+
def : InstRW<[WriteAdr, V2Write_7cyc_4L],
17591759
(instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;
17601760

17611761
// ASIMD load, 1 element, multiple, 4 reg, Q-form
17621762
def : InstRW<[V2Write_7cyc_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;
1763-
def : InstRW<[V2Write_7cyc_4L, WriteAdr],
1763+
def : InstRW<[WriteAdr, V2Write_7cyc_4L],
17641764
(instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;
17651765

17661766
// ASIMD load, 1 element, one lane, B/H/S
17671767
// ASIMD load, 1 element, one lane, D
17681768
def : InstRW<[V2Write_8cyc_1L_1V], (instregex "LD1i(8|16|32|64)$")>;
1769-
def : InstRW<[V2Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
1769+
def : InstRW<[WriteAdr, V2Write_8cyc_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>;
17701770

17711771
// ASIMD load, 1 element, all lanes, D-form, B/H/S
17721772
// ASIMD load, 1 element, all lanes, D-form, D
17731773
def : InstRW<[V2Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>;
1774-
def : InstRW<[V2Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
1774+
def : InstRW<[WriteAdr, V2Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
17751775

17761776
// ASIMD load, 1 element, all lanes, Q-form
17771777
def : InstRW<[V2Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
1778-
def : InstRW<[V2Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
1778+
def : InstRW<[WriteAdr, V2Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
17791779

17801780
// ASIMD load, 2 element, multiple, D-form, B/H/S
17811781
def : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>;
1782-
def : InstRW<[V2Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
1782+
def : InstRW<[WriteAdr, V2Write_8cyc_1L_2V], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
17831783

17841784
// ASIMD load, 2 element, multiple, Q-form, B/H/S
17851785
// ASIMD load, 2 element, multiple, Q-form, D
17861786
def : InstRW<[V2Write_8cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
1787-
def : InstRW<[V2Write_8cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
1787+
def : InstRW<[WriteAdr, V2Write_8cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
17881788

17891789
// ASIMD load, 2 element, one lane, B/H
17901790
// ASIMD load, 2 element, one lane, S
17911791
// ASIMD load, 2 element, one lane, D
17921792
def : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2i(8|16|32|64)$")>;
1793-
def : InstRW<[V2Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>;
1793+
def : InstRW<[WriteAdr, V2Write_8cyc_1L_2V], (instregex "LD2i(8|16|32|64)_POST$")>;
17941794

17951795
// ASIMD load, 2 element, all lanes, D-form, B/H/S
17961796
// ASIMD load, 2 element, all lanes, D-form, D
17971797
def : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
1798-
def : InstRW<[V2Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
1798+
def : InstRW<[WriteAdr, V2Write_8cyc_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
17991799

18001800
// ASIMD load, 2 element, all lanes, Q-form
18011801
def : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
1802-
def : InstRW<[V2Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
1802+
def : InstRW<[WriteAdr, V2Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
18031803

18041804
// ASIMD load, 3 element, multiple, D-form, B/H/S
18051805
def : InstRW<[V2Write_8cyc_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>;
1806-
def : InstRW<[V2Write_8cyc_2L_3V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
1806+
def : InstRW<[WriteAdr, V2Write_8cyc_2L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
18071807

18081808
// ASIMD load, 3 element, multiple, Q-form, B/H/S
18091809
// ASIMD load, 3 element, multiple, Q-form, D
18101810
def : InstRW<[V2Write_8cyc_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
1811-
def : InstRW<[V2Write_8cyc_3L_3V, WriteAdr], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;
1811+
def : InstRW<[WriteAdr, V2Write_8cyc_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;
18121812

18131813
// ASIMD load, 3 element, one lane, B/H
18141814
// ASIMD load, 3 element, one lane, S
18151815
// ASIMD load, 3 element, one lane, D
18161816
def : InstRW<[V2Write_8cyc_2L_3V], (instregex "LD3i(8|16|32|64)$")>;
1817-
def : InstRW<[V2Write_8cyc_2L_3V, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
1817+
def : InstRW<[WriteAdr, V2Write_8cyc_2L_3V], (instregex "LD3i(8|16|32|64)_POST$")>;
18181818

18191819
// ASIMD load, 3 element, all lanes, D-form, B/H/S
18201820
// ASIMD load, 3 element, all lanes, D-form, D
18211821
def : InstRW<[V2Write_8cyc_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
1822-
def : InstRW<[V2Write_8cyc_2L_3V, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
1822+
def : InstRW<[WriteAdr, V2Write_8cyc_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
18231823

18241824
// ASIMD load, 3 element, all lanes, Q-form, B/H/S
18251825
// ASIMD load, 3 element, all lanes, Q-form, D
18261826
def : InstRW<[V2Write_8cyc_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
1827-
def : InstRW<[V2Write_8cyc_3L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
1827+
def : InstRW<[WriteAdr, V2Write_8cyc_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
18281828

18291829
// ASIMD load, 4 element, multiple, D-form, B/H/S
18301830
def : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>;
1831-
def : InstRW<[V2Write_8cyc_3L_4V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
1831+
def : InstRW<[WriteAdr, V2Write_8cyc_3L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
18321832

18331833
// ASIMD load, 4 element, multiple, Q-form, B/H/S
18341834
// ASIMD load, 4 element, multiple, Q-form, D
18351835
def : InstRW<[V2Write_9cyc_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
1836-
def : InstRW<[V2Write_9cyc_6L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
1836+
def : InstRW<[WriteAdr, V2Write_9cyc_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
18371837

18381838
// ASIMD load, 4 element, one lane, B/H
18391839
// ASIMD load, 4 element, one lane, S
18401840
// ASIMD load, 4 element, one lane, D
18411841
def : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4i(8|16|32|64)$")>;
1842-
def : InstRW<[V2Write_8cyc_3L_4V, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
1842+
def : InstRW<[WriteAdr, V2Write_8cyc_3L_4V], (instregex "LD4i(8|16|32|64)_POST$")>;
18431843

18441844
// ASIMD load, 4 element, all lanes, D-form, B/H/S
18451845
// ASIMD load, 4 element, all lanes, D-form, D
1846-
def : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
1847-
def : InstRW<[V2Write_8cyc_3L_4V, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
1846+
def : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
1847+
def : InstRW<[WriteAdr, V2Write_8cyc_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
18481848

18491849
// ASIMD load, 4 element, all lanes, Q-form, B/H/S
18501850
// ASIMD load, 4 element, all lanes, Q-form, D
1851-
def : InstRW<[V2Write_8cyc_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
1852-
def : InstRW<[V2Write_8cyc_4L_4V, WriteAdr], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
1851+
def : InstRW<[V2Write_8cyc_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
1852+
def : InstRW<[WriteAdr, V2Write_8cyc_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
18531853

18541854
// ASIMD store instructions
18551855
// -----------------------------------------------------------------------------
18561856

18571857
// ASIMD store, 1 element, multiple, 1 reg, D-form
18581858
def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
1859-
def : InstRW<[V2Write_2cyc_1L01_1V01, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
1859+
def : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
18601860

18611861
// ASIMD store, 1 element, multiple, 1 reg, Q-form
18621862
def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
1863-
def : InstRW<[V2Write_2cyc_1L01_1V01, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
1863+
def : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
18641864

18651865
// ASIMD store, 1 element, multiple, 2 reg, D-form
18661866
def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
1867-
def : InstRW<[V2Write_2cyc_1L01_1V01, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
1867+
def : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
18681868

18691869
// ASIMD store, 1 element, multiple, 2 reg, Q-form
18701870
def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
1871-
def : InstRW<[V2Write_2cyc_2L01_2V01, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
1871+
def : InstRW<[WriteAdr, V2Write_2cyc_2L01_2V01], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
18721872

18731873
// ASIMD store, 1 element, multiple, 3 reg, D-form
18741874
def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
1875-
def : InstRW<[V2Write_2cyc_2L01_2V01, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
1875+
def : InstRW<[WriteAdr, V2Write_2cyc_2L01_2V01], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
18761876

18771877
// ASIMD store, 1 element, multiple, 3 reg, Q-form
18781878
def : InstRW<[V2Write_2cyc_3L01_3V01], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
1879-
def : InstRW<[V2Write_2cyc_3L01_3V01, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
1879+
def : InstRW<[WriteAdr, V2Write_2cyc_3L01_3V01], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
18801880

18811881
// ASIMD store, 1 element, multiple, 4 reg, D-form
18821882
def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
1883-
def : InstRW<[V2Write_2cyc_2L01_2V01, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
1883+
def : InstRW<[WriteAdr, V2Write_2cyc_2L01_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
18841884

18851885
// ASIMD store, 1 element, multiple, 4 reg, Q-form
18861886
def : InstRW<[V2Write_2cyc_4L01_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
1887-
def : InstRW<[V2Write_2cyc_4L01_4V01, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
1887+
def : InstRW<[WriteAdr, V2Write_2cyc_4L01_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
18881888

18891889
// ASIMD store, 1 element, one lane, B/H/S
18901890
// ASIMD store, 1 element, one lane, D
18911891
def : InstRW<[V2Write_4cyc_1L01_2V01], (instregex "ST1i(8|16|32|64)$")>;
1892-
def : InstRW<[V2Write_4cyc_1L01_2V01, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
1892+
def : InstRW<[WriteAdr, V2Write_4cyc_1L01_2V01], (instregex "ST1i(8|16|32|64)_POST$")>;
18931893

18941894
// ASIMD store, 2 element, multiple, D-form, B/H/S
18951895
def : InstRW<[V2Write_4cyc_1L01_2V01], (instregex "ST2Twov(8b|4h|2s)$")>;
1896-
def : InstRW<[V2Write_4cyc_1L01_2V01, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
1896+
def : InstRW<[WriteAdr, V2Write_4cyc_1L01_2V01], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
18971897

18981898
// ASIMD store, 2 element, multiple, Q-form, B/H/S
18991899
// ASIMD store, 2 element, multiple, Q-form, D
19001900
def : InstRW<[V2Write_4cyc_2L01_4V01], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
1901-
def : InstRW<[V2Write_4cyc_2L01_4V01, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
1901+
def : InstRW<[WriteAdr, V2Write_4cyc_2L01_4V01], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
19021902

19031903
// ASIMD store, 2 element, one lane, B/H/S
19041904
// ASIMD store, 2 element, one lane, D
19051905
def : InstRW<[V2Write_4cyc_1L01_2V01], (instregex "ST2i(8|16|32|64)$")>;
1906-
def : InstRW<[V2Write_4cyc_1L01_2V01, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
1906+
def : InstRW<[WriteAdr, V2Write_4cyc_1L01_2V01], (instregex "ST2i(8|16|32|64)_POST$")>;
19071907

19081908
// ASIMD store, 3 element, multiple, D-form, B/H/S
19091909
def : InstRW<[V2Write_5cyc_2L01_4V01], (instregex "ST3Threev(8b|4h|2s)$")>;
1910-
def : InstRW<[V2Write_5cyc_2L01_4V01, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
1910+
def : InstRW<[WriteAdr, V2Write_5cyc_2L01_4V01], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
19111911

19121912
// ASIMD store, 3 element, multiple, Q-form, B/H/S
19131913
// ASIMD store, 3 element, multiple, Q-form, D
19141914
def : InstRW<[V2Write_6cyc_3L01_6V01], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
1915-
def : InstRW<[V2Write_6cyc_3L01_6V01, WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
1915+
def : InstRW<[WriteAdr, V2Write_6cyc_3L01_6V01], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
19161916

19171917
// ASIMD store, 3 element, one lane, B/H
19181918
// ASIMD store, 3 element, one lane, S
19191919
// ASIMD store, 3 element, one lane, D
19201920
def : InstRW<[V2Write_5cyc_2L01_4V01], (instregex "ST3i(8|16|32|64)$")>;
1921-
def : InstRW<[V2Write_5cyc_2L01_4V01, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
1921+
def : InstRW<[WriteAdr, V2Write_5cyc_2L01_4V01], (instregex "ST3i(8|16|32|64)_POST$")>;
19221922

19231923
// ASIMD store, 4 element, multiple, D-form, B/H/S
19241924
def : InstRW<[V2Write_6cyc_2L01_6V01], (instregex "ST4Fourv(8b|4h|2s)$")>;
1925-
def : InstRW<[V2Write_6cyc_2L01_6V01, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
1925+
def : InstRW<[WriteAdr, V2Write_6cyc_2L01_6V01], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
19261926

19271927
// ASIMD store, 4 element, multiple, Q-form, B/H/S
19281928
def : InstRW<[V2Write_7cyc_4L01_12V01], (instregex "ST4Fourv(16b|8h|4s)$")>;
1929-
def : InstRW<[V2Write_7cyc_4L01_12V01, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
1929+
def : InstRW<[WriteAdr, V2Write_7cyc_4L01_12V01], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
19301930

19311931
// ASIMD store, 4 element, multiple, Q-form, D
19321932
def : InstRW<[V2Write_5cyc_4L01_8V01], (instregex "ST4Fourv(2d)$")>;
1933-
def : InstRW<[V2Write_5cyc_4L01_8V01, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
1933+
def : InstRW<[WriteAdr, V2Write_5cyc_4L01_8V01], (instregex "ST4Fourv(2d)_POST$")>;
19341934

19351935
// ASIMD store, 4 element, one lane, B/H/S
19361936
def : InstRW<[V2Write_6cyc_1L01_3V01], (instregex "ST4i(8|16|32)$")>;
1937-
def : InstRW<[V2Write_6cyc_1L01_3V01, WriteAdr], (instregex "ST4i(8|16|32)_POST$")>;
1937+
def : InstRW<[WriteAdr, V2Write_6cyc_1L01_3V01], (instregex "ST4i(8|16|32)_POST$")>;
19381938

19391939
// ASIMD store, 4 element, one lane, D
19401940
def : InstRW<[V2Write_4cyc_2L01_4V01], (instregex "ST4i(64)$")>;
1941-
def : InstRW<[V2Write_4cyc_2L01_4V01, WriteAdr], (instregex "ST4i(64)_POST$")>;
1941+
def : InstRW<[WriteAdr, V2Write_4cyc_2L01_4V01], (instregex "ST4i(64)_POST$")>;
19421942

19431943
// Cryptography extensions
19441944
// -----------------------------------------------------------------------------

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