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[X86] ptest.ll - add test coverage for #144861 load chains
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‎llvm/test/CodeGen/X86/ptest.ll

Lines changed: 164 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2,-avx | FileCheck %s --check-prefix=SSE2
3-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1,-avx | FileCheck %s --check-prefix=SSE41
4-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,-avx2 | FileCheck %s --check-prefixes=AVX,AVX1
5-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512dq,+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512
2+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2,-avx | FileCheck %s --check-prefixes=CHECK,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1,-avx | FileCheck %s --check-prefixes=CHECK,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,-avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512dq,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
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define i32 @veccond128(<4 x i32> %input) {
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; SSE2-LABEL: veccond128:
@@ -388,3 +388,163 @@ define i32 @vecsel512(<16 x i32> %input, i32 %a, i32 %b) {
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%t2 = select i1 %t1, i32 %a, i32 %b
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ret i32 %t2
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}
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define i1 @vecmp_load64x2(ptr %p0) {
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; CHECK-LABEL: vecmp_load64x2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: orq 8(%rdi), %rax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%p1 = getelementptr i8, ptr %p0, i64 8
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%i0 = load i64, ptr %p0, align 1
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%i1 = load i64, ptr %p1, align 1
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%or = or i64 %i0, %i1
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%ne = icmp ne i64 %or, 0
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%zx = zext i1 %ne to i32
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%eq = icmp eq i32 %zx, 0
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ret i1 %eq
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}
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define i1 @vecmp_load64x4(ptr %p0) {
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; CHECK-LABEL: vecmp_load64x4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rcx
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; CHECK-NEXT: orq 16(%rdi), %rax
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; CHECK-NEXT: orq 24(%rdi), %rcx
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; CHECK-NEXT: orq %rax, %rcx
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%p1 = getelementptr i8, ptr %p0, i64 8
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%p2 = getelementptr i8, ptr %p0, i64 16
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%p3 = getelementptr i8, ptr %p0, i64 24
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%i0 = load i64, ptr %p0, align 1
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%i1 = load i64, ptr %p1, align 1
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%i2 = load i64, ptr %p2, align 1
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%i3 = load i64, ptr %p3, align 1
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%or02 = or i64 %i0, %i2
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%or13 = or i64 %i1, %i3
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%or = or i64 %or02, %or13
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%ne = icmp ne i64 %or, 0
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%zx = zext i1 %ne to i32
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%eq = icmp eq i32 %zx, 0
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ret i1 %eq
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}
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define i1 @vecmp_load128x2(ptr %p0) {
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; CHECK-LABEL: vecmp_load128x2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rcx
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; CHECK-NEXT: orq 24(%rdi), %rcx
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; CHECK-NEXT: orq 16(%rdi), %rax
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; CHECK-NEXT: orq %rcx, %rax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%p1 = getelementptr i8, ptr %p0, i64 16
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%i0 = load i128, ptr %p0, align 1
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%i1 = load i128, ptr %p1, align 1
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%or = or i128 %i0, %i1
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%ne = icmp ne i128 %or, 0
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%zx = zext i1 %ne to i32
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%eq = icmp eq i32 %zx, 0
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ret i1 %eq
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}
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define i1 @vecmp_load128x4(ptr %p0) {
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; CHECK-LABEL: vecmp_load128x4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rcx
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; CHECK-NEXT: movq 24(%rdi), %rdx
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; CHECK-NEXT: movq 16(%rdi), %rsi
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; CHECK-NEXT: orq 32(%rdi), %rax
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; CHECK-NEXT: orq 40(%rdi), %rcx
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; CHECK-NEXT: orq 48(%rdi), %rsi
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; CHECK-NEXT: orq %rax, %rsi
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; CHECK-NEXT: orq 56(%rdi), %rdx
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; CHECK-NEXT: orq %rcx, %rdx
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; CHECK-NEXT: orq %rsi, %rdx
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%p1 = getelementptr i8, ptr %p0, i64 16
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%p2 = getelementptr i8, ptr %p0, i64 32
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%p3 = getelementptr i8, ptr %p0, i64 48
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%i0 = load i128, ptr %p0, align 1
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%i1 = load i128, ptr %p1, align 1
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%i2 = load i128, ptr %p2, align 1
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%i3 = load i128, ptr %p3, align 1
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%or02 = or i128 %i0, %i2
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%or13 = or i128 %i1, %i3
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%or = or i128 %or02, %or13
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%ne = icmp ne i128 %or, 0
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%zx = zext i1 %ne to i32
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%eq = icmp eq i32 %zx, 0
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ret i1 %eq
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}
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; PR144861
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define i1 @vecmp_load256x2(ptr %p0) {
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; CHECK-LABEL: vecmp_load256x2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq 24(%rdi), %rax
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; CHECK-NEXT: movq (%rdi), %rcx
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: movq 16(%rdi), %rsi
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; CHECK-NEXT: orq 48(%rdi), %rsi
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; CHECK-NEXT: orq 32(%rdi), %rcx
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; CHECK-NEXT: orq %rsi, %rcx
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; CHECK-NEXT: orq 56(%rdi), %rax
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; CHECK-NEXT: orq 40(%rdi), %rdx
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; CHECK-NEXT: orq %rax, %rdx
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; CHECK-NEXT: orq %rcx, %rdx
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%p1 = getelementptr i8, ptr %p0, i64 32
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%i0 = load i256, ptr %p0, align 1
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%i1 = load i256, ptr %p1, align 1
507+
%or = or i256 %i0, %i1
508+
%ne = icmp ne i256 %or, 0
509+
%zx = zext i1 %ne to i32
510+
%eq = icmp eq i32 %zx, 0
511+
ret i1 %eq
512+
}
513+
514+
define i1 @vecmp_load512x2(ptr %p0) {
515+
; CHECK-LABEL: vecmp_load512x2:
516+
; CHECK: # %bb.0:
517+
; CHECK-NEXT: movq 24(%rdi), %rax
518+
; CHECK-NEXT: movq 56(%rdi), %rdx
519+
; CHECK-NEXT: movq 40(%rdi), %rsi
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; CHECK-NEXT: movq 16(%rdi), %rcx
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; CHECK-NEXT: movq 48(%rdi), %r8
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; CHECK-NEXT: movq (%rdi), %r9
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; CHECK-NEXT: movq 8(%rdi), %r10
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; CHECK-NEXT: movq 32(%rdi), %r11
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; CHECK-NEXT: orq 96(%rdi), %r11
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; CHECK-NEXT: orq 64(%rdi), %r9
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; CHECK-NEXT: orq %r11, %r9
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; CHECK-NEXT: orq 112(%rdi), %r8
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; CHECK-NEXT: orq 80(%rdi), %rcx
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; CHECK-NEXT: orq %r8, %rcx
531+
; CHECK-NEXT: orq %r9, %rcx
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; CHECK-NEXT: orq 104(%rdi), %rsi
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; CHECK-NEXT: orq 72(%rdi), %r10
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; CHECK-NEXT: orq %rsi, %r10
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; CHECK-NEXT: orq 120(%rdi), %rdx
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; CHECK-NEXT: orq 88(%rdi), %rax
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; CHECK-NEXT: orq %rdx, %rax
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; CHECK-NEXT: orq %r10, %rax
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; CHECK-NEXT: orq %rcx, %rax
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; CHECK-NEXT: sete %al
541+
; CHECK-NEXT: retq
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%p1 = getelementptr i8, ptr %p0, i64 64
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%i0 = load i512, ptr %p0, align 1
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%i1 = load i512, ptr %p1, align 1
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%or = or i512 %i0, %i1
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%ne = icmp ne i512 %or, 0
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%zx = zext i1 %ne to i32
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%eq = icmp eq i32 %zx, 0
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ret i1 %eq
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}

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