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[DAGCombiner] Add pre-commit tests. NFC.
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‎llvm/test/CodeGen/AArch64/trunc-nsw-nuw.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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define zeroext i32 @trunc_nuw_nsw_urem(i64 %x) nounwind {
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; CHECK-LABEL: trunc_nuw_nsw_urem:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #5977 // =0x1759
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; CHECK-NEXT: mov w9, w0
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; CHECK-NEXT: movk w8, #53687, lsl #16
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; CHECK-NEXT: umull x8, w9, w8
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; CHECK-NEXT: mov w9, #10000 // =0x2710
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; CHECK-NEXT: lsr x8, x8, #45
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; CHECK-NEXT: msub w0, w8, w9, w0
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; CHECK-NEXT: ret
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entry:
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%trunc = trunc nuw nsw i64 %x to i32
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%rem = urem i32 %trunc, 10000
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ret i32 %rem
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}
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define i64 @zext_nneg_udiv_trunc_nuw(i64 %x) nounwind {
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; CHECK-LABEL: zext_nneg_udiv_trunc_nuw:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #52429 // =0xcccd
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; CHECK-NEXT: and w9, w0, #0xffff
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; CHECK-NEXT: mul w8, w9, w8
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; CHECK-NEXT: lsr w0, w8, #23
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; CHECK-NEXT: ret
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entry:
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%trunc = trunc nuw i64 %x to i16
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%div = udiv i16 %trunc, 160
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%ext = zext nneg i16 %div to i64
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ret i64 %ext
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}
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define i64 @sext_udiv_trunc_nuw(i64 %x) nounwind {
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; CHECK-LABEL: sext_udiv_trunc_nuw:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #52429 // =0xcccd
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; CHECK-NEXT: and w9, w0, #0xffff
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; CHECK-NEXT: mul w8, w9, w8
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; CHECK-NEXT: lsr w0, w8, #23
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; CHECK-NEXT: ret
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entry:
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%trunc = trunc nuw i64 %x to i16
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%div = udiv i16 %trunc, 160
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%ext = sext i16 %div to i64
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ret i64 %ext
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}
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define ptr @gep_nusw_zext_nneg_add_trunc_nuw_nsw(ptr %p, i64 %x) nounwind {
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; CHECK-LABEL: gep_nusw_zext_nneg_add_trunc_nuw_nsw:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add w8, w1, #5
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; CHECK-NEXT: add x0, x0, w8, uxtw #2
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; CHECK-NEXT: ret
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entry:
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%trunc = trunc nuw nsw i64 %x to i32
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%add = add nuw nsw i32 %trunc, 5
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%offset = zext nneg i32 %add to i64
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%gep = getelementptr nusw float, ptr %p, i64 %offset
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ret ptr %gep
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}

‎llvm/test/CodeGen/RISCV/trunc-nsw-nuw.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s
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define signext i8 @trunc_nsw_add(i32 signext %x) nounwind {
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; CHECK-LABEL: trunc_nsw_add:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi a0, a0, 1
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; CHECK-NEXT: slli a0, a0, 56
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; CHECK-NEXT: srai a0, a0, 56
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; CHECK-NEXT: ret
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entry:
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%add = add nsw i32 %x, 1
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%trunc = trunc nsw i32 %add to i8
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ret i8 %trunc
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}
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define signext i32 @trunc_nuw_nsw_urem(i64 %x) nounwind {
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; CHECK-LABEL: trunc_nuw_nsw_urem:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: slli a1, a0, 32
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; CHECK-NEXT: lui a2, 858993
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; CHECK-NEXT: addi a2, a2, 1881
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; CHECK-NEXT: slli a2, a2, 32
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; CHECK-NEXT: mulhu a1, a1, a2
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; CHECK-NEXT: srli a1, a1, 45
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; CHECK-NEXT: lui a2, 2
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; CHECK-NEXT: addi a2, a2, 1808
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; CHECK-NEXT: mul a1, a1, a2
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; CHECK-NEXT: subw a0, a0, a1
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; CHECK-NEXT: ret
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entry:
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%trunc = trunc nuw nsw i64 %x to i32
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%rem = urem i32 %trunc, 10000
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ret i32 %rem
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}
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define i64 @zext_nneg_udiv_trunc_nuw(i64 %x) nounwind {
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; CHECK-LABEL: zext_nneg_udiv_trunc_nuw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a1, 52429
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; CHECK-NEXT: slli a1, a1, 4
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; CHECK-NEXT: slli a0, a0, 48
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; CHECK-NEXT: mulhu a0, a0, a1
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; CHECK-NEXT: srli a0, a0, 23
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; CHECK-NEXT: ret
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entry:
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%trunc = trunc nuw i64 %x to i16
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%div = udiv i16 %trunc, 160
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%ext = zext nneg i16 %div to i64
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ret i64 %ext
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}
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define i64 @sext_udiv_trunc_nuw(i64 %x) nounwind {
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; CHECK-LABEL: sext_udiv_trunc_nuw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a1, 52429
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; CHECK-NEXT: slli a1, a1, 4
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; CHECK-NEXT: slli a0, a0, 48
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; CHECK-NEXT: mulhu a0, a0, a1
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; CHECK-NEXT: srli a0, a0, 23
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; CHECK-NEXT: ret
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entry:
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%trunc = trunc nuw i64 %x to i16
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%div = udiv i16 %trunc, 160
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%ext = sext i16 %div to i64
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ret i64 %ext
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}
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define ptr @gep_nusw_zext_nneg_add_trunc_nuw_nsw(ptr %p, i64 %x) nounwind {
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; CHECK-LABEL: gep_nusw_zext_nneg_add_trunc_nuw_nsw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sext.w a1, a1
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; CHECK-NEXT: slli a1, a1, 2
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; CHECK-NEXT: add a0, a1, a0
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; CHECK-NEXT: addi a0, a0, 20
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; CHECK-NEXT: ret
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entry:
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%trunc = trunc nuw nsw i64 %x to i32
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%add = add nuw nsw i32 %trunc, 5
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%offset = zext nneg i32 %add to i64
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%gep = getelementptr nusw float, ptr %p, i64 %offset
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ret ptr %gep
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}

‎llvm/test/CodeGen/X86/trunc-nsw-nuw.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=x86_64 | FileCheck %s
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define zeroext i32 @trunc_nuw_nsw_urem(i64 %x) nounwind {
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; CHECK-LABEL: trunc_nuw_nsw_urem:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: movl $3518437209, %edx # imm = 0xD1B71759
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; CHECK-NEXT: imulq %rcx, %rdx
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; CHECK-NEXT: shrq $45, %rdx
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; CHECK-NEXT: imull $10000, %edx, %ecx # imm = 0x2710
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
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; CHECK-NEXT: retq
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entry:
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%trunc = trunc nuw nsw i64 %x to i32
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%rem = urem i32 %trunc, 10000
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ret i32 %rem
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}
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define i64 @zext_nneg_udiv_trunc_nuw(i64 %x) nounwind {
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; CHECK-LABEL: zext_nneg_udiv_trunc_nuw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movzwl %di, %eax
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; CHECK-NEXT: imull $52429, %eax, %eax # imm = 0xCCCD
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; CHECK-NEXT: shrl $23, %eax
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; CHECK-NEXT: retq
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entry:
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%trunc = trunc nuw i64 %x to i16
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%div = udiv i16 %trunc, 160
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%ext = zext nneg i16 %div to i64
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ret i64 %ext
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}
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define i64 @sext_udiv_trunc_nuw(i64 %x) nounwind {
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; CHECK-LABEL: sext_udiv_trunc_nuw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movzwl %di, %eax
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; CHECK-NEXT: imull $52429, %eax, %eax # imm = 0xCCCD
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; CHECK-NEXT: shrl $23, %eax
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; CHECK-NEXT: retq
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entry:
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%trunc = trunc nuw i64 %x to i16
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%div = udiv i16 %trunc, 160
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%ext = sext i16 %div to i64
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ret i64 %ext
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}
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define ptr @gep_nusw_zext_nneg_add_trunc_nuw_nsw(ptr %p, i64 %x) nounwind {
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; CHECK-LABEL: gep_nusw_zext_nneg_add_trunc_nuw_nsw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: leaq 20(%rdi,%rax,4), %rax
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; CHECK-NEXT: retq
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entry:
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%trunc = trunc nuw nsw i64 %x to i32
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%add = add nuw nsw i32 %trunc, 5
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%offset = zext nneg i32 %add to i64
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%gep = getelementptr nusw float, ptr %p, i64 %offset
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ret ptr %gep
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}

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