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| 1 | +//===- SMEPeepholeOpt.cpp - SME peephole optimization pass-----------------===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | +// This pass tries to remove back-to-back (smstart, smstop) and |
| 9 | +// (smstop, smstart) sequences. The pass is conservative when it cannot |
| 10 | +// determine that it is safe to remove these sequences. |
| 11 | +//===----------------------------------------------------------------------===// |
| 12 | + |
| 13 | +#include "AArch64InstrInfo.h" |
| 14 | +#include "AArch64MachineFunctionInfo.h" |
| 15 | +#include "AArch64Subtarget.h" |
| 16 | +#include "Utils/AArch64SMEAttributes.h" |
| 17 | +#include "llvm/ADT/SmallVector.h" |
| 18 | +#include "llvm/CodeGen/MachineBasicBlock.h" |
| 19 | +#include "llvm/CodeGen/MachineFunctionPass.h" |
| 20 | + |
| 21 | +using namespace llvm; |
| 22 | + |
| 23 | +#define DEBUG_TYPE "aarch64-sme-peephole-opt" |
| 24 | + |
| 25 | +namespace { |
| 26 | + |
| 27 | +struct SMEPeepholeOpt : public MachineFunctionPass { |
| 28 | + static char ID; |
| 29 | + |
| 30 | + SMEPeepholeOpt() : MachineFunctionPass(ID) { |
| 31 | + initializeSMEPeepholeOptPass(*PassRegistry::getPassRegistry()); |
| 32 | + } |
| 33 | + |
| 34 | + bool runOnMachineFunction(MachineFunction &MF) override; |
| 35 | + |
| 36 | + StringRef getPassName() const override { |
| 37 | + return "SME Peephole Optimization pass"; |
| 38 | + } |
| 39 | + |
| 40 | + void getAnalysisUsage(AnalysisUsage &AU) const override { |
| 41 | + AU.setPreservesCFG(); |
| 42 | + MachineFunctionPass::getAnalysisUsage(AU); |
| 43 | + } |
| 44 | + |
| 45 | + bool optimizeStartStopPairs(MachineBasicBlock &MBB, |
| 46 | + bool &HasRemainingSMChange) const; |
| 47 | +}; |
| 48 | + |
| 49 | +char SMEPeepholeOpt::ID = 0; |
| 50 | + |
| 51 | +} // end anonymous namespace |
| 52 | + |
| 53 | +static bool isConditionalStartStop(const MachineInstr *MI) { |
| 54 | + return MI->getOpcode() == AArch64::MSRpstatePseudo; |
| 55 | +} |
| 56 | + |
| 57 | +static bool isMatchingStartStopPair(const MachineInstr *MI1, |
| 58 | + const MachineInstr *MI2) { |
| 59 | + // We only consider the same type of streaming mode change here, i.e. |
| 60 | + // start/stop SM, or start/stop ZA pairs. |
| 61 | + if (MI1->getOperand(0).getImm() != MI2->getOperand(0).getImm()) |
| 62 | + return false; |
| 63 | + |
| 64 | + // One must be 'start', the other must be 'stop' |
| 65 | + if (MI1->getOperand(1).getImm() == MI2->getOperand(1).getImm()) |
| 66 | + return false; |
| 67 | + |
| 68 | + bool IsConditional = isConditionalStartStop(MI2); |
| 69 | + if (isConditionalStartStop(MI1) != IsConditional) |
| 70 | + return false; |
| 71 | + |
| 72 | + if (!IsConditional) |
| 73 | + return true; |
| 74 | + |
| 75 | + // Check to make sure the conditional start/stop pairs are identical. |
| 76 | + if (MI1->getOperand(2).getImm() != MI2->getOperand(2).getImm()) |
| 77 | + return false; |
| 78 | + |
| 79 | + // Ensure reg masks are identical. |
| 80 | + if (MI1->getOperand(4).getRegMask() != MI2->getOperand(4).getRegMask()) |
| 81 | + return false; |
| 82 | + |
| 83 | + // This optimisation is unlikely to happen in practice for conditional |
| 84 | + // smstart/smstop pairs as the virtual registers for pstate.sm will always |
| 85 | + // be different. |
| 86 | + // TODO: For this optimisation to apply to conditional smstart/smstop, |
| 87 | + // this pass will need to do more work to remove redundant calls to |
| 88 | + // __arm_sme_state. |
| 89 | + |
| 90 | + // Only consider conditional start/stop pairs which read the same register |
| 91 | + // holding the original value of pstate.sm, as some conditional start/stops |
| 92 | + // require the state on entry to the function. |
| 93 | + if (MI1->getOperand(3).isReg() && MI2->getOperand(3).isReg()) { |
| 94 | + Register Reg1 = MI1->getOperand(3).getReg(); |
| 95 | + Register Reg2 = MI2->getOperand(3).getReg(); |
| 96 | + if (Reg1.isPhysical() || Reg2.isPhysical() || Reg1 != Reg2) |
| 97 | + return false; |
| 98 | + } |
| 99 | + |
| 100 | + return true; |
| 101 | +} |
| 102 | + |
| 103 | +static bool ChangesStreamingMode(const MachineInstr *MI) { |
| 104 | + assert((MI->getOpcode() == AArch64::MSRpstatesvcrImm1 || |
| 105 | + MI->getOpcode() == AArch64::MSRpstatePseudo) && |
| 106 | + "Expected MI to be a smstart/smstop instruction"); |
| 107 | + return MI->getOperand(0).getImm() == AArch64SVCR::SVCRSM || |
| 108 | + MI->getOperand(0).getImm() == AArch64SVCR::SVCRSMZA; |
| 109 | +} |
| 110 | + |
| 111 | +bool SMEPeepholeOpt::optimizeStartStopPairs(MachineBasicBlock &MBB, |
| 112 | + bool &HasRemainingSMChange) const { |
| 113 | + SmallVector<MachineInstr *, 4> ToBeRemoved; |
| 114 | + |
| 115 | + bool Changed = false; |
| 116 | + MachineInstr *Prev = nullptr; |
| 117 | + HasRemainingSMChange = false; |
| 118 | + |
| 119 | + auto Reset = [&]() { |
| 120 | + if (Prev && ChangesStreamingMode(Prev)) |
| 121 | + HasRemainingSMChange = true; |
| 122 | + Prev = nullptr; |
| 123 | + ToBeRemoved.clear(); |
| 124 | + }; |
| 125 | + |
| 126 | + // Walk through instructions in the block trying to find pairs of smstart |
| 127 | + // and smstop nodes that cancel each other out. We only permit a limited |
| 128 | + // set of instructions to appear between them, otherwise we reset our |
| 129 | + // tracking. |
| 130 | + for (MachineInstr &MI : make_early_inc_range(MBB)) { |
| 131 | + switch (MI.getOpcode()) { |
| 132 | + default: |
| 133 | + Reset(); |
| 134 | + break; |
| 135 | + case AArch64::COPY: { |
| 136 | + // Permit copies of 32 and 64-bit registers. |
| 137 | + if (!MI.getOperand(1).isReg()) { |
| 138 | + Reset(); |
| 139 | + break; |
| 140 | + } |
| 141 | + Register Reg = MI.getOperand(1).getReg(); |
| 142 | + if (!AArch64::GPR32RegClass.contains(Reg) && |
| 143 | + !AArch64::GPR64RegClass.contains(Reg)) |
| 144 | + Reset(); |
| 145 | + break; |
| 146 | + } |
| 147 | + case AArch64::ADJCALLSTACKDOWN: |
| 148 | + case AArch64::ADJCALLSTACKUP: |
| 149 | + case AArch64::ANDXri: |
| 150 | + case AArch64::ADDXri: |
| 151 | + // We permit these as they don't generate SVE/NEON instructions. |
| 152 | + break; |
| 153 | + case AArch64::VGRestorePseudo: |
| 154 | + case AArch64::VGSavePseudo: |
| 155 | + // When the smstart/smstop are removed, we should also remove |
| 156 | + // the pseudos that save/restore the VG value for CFI info. |
| 157 | + ToBeRemoved.push_back(&MI); |
| 158 | + break; |
| 159 | + case AArch64::MSRpstatesvcrImm1: |
| 160 | + case AArch64::MSRpstatePseudo: { |
| 161 | + if (!Prev) |
| 162 | + Prev = &MI; |
| 163 | + else if (isMatchingStartStopPair(Prev, &MI)) { |
| 164 | + // If they match, we can remove them, and possibly any instructions |
| 165 | + // that we marked for deletion in between. |
| 166 | + Prev->eraseFromParent(); |
| 167 | + MI.eraseFromParent(); |
| 168 | + for (MachineInstr *TBR : ToBeRemoved) |
| 169 | + TBR->eraseFromParent(); |
| 170 | + ToBeRemoved.clear(); |
| 171 | + Prev = nullptr; |
| 172 | + Changed = true; |
| 173 | + } else { |
| 174 | + Reset(); |
| 175 | + Prev = &MI; |
| 176 | + } |
| 177 | + break; |
| 178 | + } |
| 179 | + } |
| 180 | + } |
| 181 | + |
| 182 | + return Changed; |
| 183 | +} |
| 184 | + |
| 185 | +INITIALIZE_PASS(SMEPeepholeOpt, "aarch64-sme-peephole-opt", |
| 186 | + "SME Peephole Optimization", false, false) |
| 187 | + |
| 188 | +bool SMEPeepholeOpt::runOnMachineFunction(MachineFunction &MF) { |
| 189 | + if (skipFunction(MF.getFunction())) |
| 190 | + return false; |
| 191 | + |
| 192 | + if (!MF. getSubtarget<AArch64Subtarget>(). hasSME()) |
| 193 | + return false; |
| 194 | + |
| 195 | + assert(MF.getRegInfo().isSSA() && "Expected to be run on SSA form!"); |
| 196 | + |
| 197 | + bool Changed = false; |
| 198 | + bool FunctionHasRemainingSMChange = false; |
| 199 | + |
| 200 | + // Even if the block lives in a function with no SME attributes attached we |
| 201 | + // still have to analyze all the blocks because we may call a streaming |
| 202 | + // function that requires smstart/smstop pairs. |
| 203 | + for (MachineBasicBlock &MBB : MF) { |
| 204 | + bool BlockHasRemainingSMChange; |
| 205 | + Changed |= optimizeStartStopPairs(MBB, BlockHasRemainingSMChange); |
| 206 | + FunctionHasRemainingSMChange |= BlockHasRemainingSMChange; |
| 207 | + } |
| 208 | + |
| 209 | + AArch64FunctionInfo *AFI = MF. getInfo<AArch64FunctionInfo>(); |
| 210 | + if (Changed && AFI->hasStreamingModeChanges()) |
| 211 | + AFI->setHasStreamingModeChanges(FunctionHasRemainingSMChange); |
| 212 | + |
| 213 | + return Changed; |
| 214 | +} |
| 215 | + |
| 216 | +FunctionPass *llvm::createSMEPeepholeOptPass() { return new SMEPeepholeOpt(); } |
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