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2 files changed

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‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 63 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -9135,67 +9135,67 @@ bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const {
91359135
}
91369136

91379137
bool SIInstrInfo::isRenamedInGFX9(int Opcode) const {
9138-
switch(Opcode) {
9139-
case AMDGPU::V_ADDC_U32_dpp:
9140-
case AMDGPU::V_ADDC_U32_e32:
9141-
case AMDGPU::V_ADDC_U32_e64:
9142-
case AMDGPU::V_ADDC_U32_e64_dpp:
9143-
case AMDGPU::V_ADDC_U32_sdwa:
9144-
//
9145-
case AMDGPU::V_ADD_CO_U32_dpp:
9146-
case AMDGPU::V_ADD_CO_U32_e32:
9147-
case AMDGPU::V_ADD_CO_U32_e64:
9148-
case AMDGPU::V_ADD_CO_U32_e64_dpp:
9149-
case AMDGPU::V_ADD_CO_U32_sdwa:
9150-
//
9151-
case AMDGPU::V_ADD_U32_dpp:
9152-
case AMDGPU::V_ADD_U32_e32:
9153-
case AMDGPU::V_ADD_U32_e64:
9154-
case AMDGPU::V_ADD_U32_e64_dpp:
9155-
case AMDGPU::V_ADD_U32_sdwa:
9156-
//
9157-
case AMDGPU::V_DIV_FIXUP_F16_gfx9_e64:
9158-
case AMDGPU::V_FMA_F16_gfx9_e64:
9159-
case AMDGPU::V_INTERP_P2_F16:
9160-
case AMDGPU::V_MAD_F16_e64:
9161-
case AMDGPU::V_MAD_U16_e64:
9162-
case AMDGPU::V_MAD_I16_e64:
9163-
//
9164-
case AMDGPU::V_SUBBREV_U32_dpp:
9165-
case AMDGPU::V_SUBBREV_U32_e32:
9166-
case AMDGPU::V_SUBBREV_U32_e64:
9167-
case AMDGPU::V_SUBBREV_U32_e64_dpp:
9168-
case AMDGPU::V_SUBBREV_U32_sdwa:
9169-
//
9170-
case AMDGPU::V_SUBB_U32_dpp:
9171-
case AMDGPU::V_SUBB_U32_e32:
9172-
case AMDGPU::V_SUBB_U32_e64:
9173-
case AMDGPU::V_SUBB_U32_e64_dpp:
9174-
case AMDGPU::V_SUBB_U32_sdwa:
9175-
//
9176-
case AMDGPU::V_SUBREV_CO_U32_dpp:
9177-
case AMDGPU::V_SUBREV_CO_U32_e32:
9178-
case AMDGPU::V_SUBREV_CO_U32_e64:
9179-
case AMDGPU::V_SUBREV_CO_U32_e64_dpp:
9180-
case AMDGPU::V_SUBREV_CO_U32_sdwa:
9181-
//
9182-
case AMDGPU::V_SUBREV_U32_dpp:
9183-
case AMDGPU::V_SUBREV_U32_e32:
9184-
case AMDGPU::V_SUBREV_U32_e64:
9185-
case AMDGPU::V_SUBREV_U32_e64_dpp:
9186-
case AMDGPU::V_SUBREV_U32_sdwa:
9187-
//
9188-
case AMDGPU::V_SUB_CO_U32_dpp:
9189-
case AMDGPU::V_SUB_CO_U32_e32:
9190-
case AMDGPU::V_SUB_CO_U32_e64:
9191-
case AMDGPU::V_SUB_CO_U32_e64_dpp:
9192-
case AMDGPU::V_SUB_CO_U32_sdwa:
9193-
//
9194-
case AMDGPU::V_SUB_U32_dpp:
9195-
case AMDGPU::V_SUB_U32_e32:
9196-
case AMDGPU::V_SUB_U32_e64:
9197-
case AMDGPU::V_SUB_U32_e64_dpp:
9198-
case AMDGPU::V_SUB_U32_sdwa:
9138+
switch (Opcode) {
9139+
case AMDGPU::V_ADDC_U32_dpp:
9140+
case AMDGPU::V_ADDC_U32_e32:
9141+
case AMDGPU::V_ADDC_U32_e64:
9142+
case AMDGPU::V_ADDC_U32_e64_dpp:
9143+
case AMDGPU::V_ADDC_U32_sdwa:
9144+
//
9145+
case AMDGPU::V_ADD_CO_U32_dpp:
9146+
case AMDGPU::V_ADD_CO_U32_e32:
9147+
case AMDGPU::V_ADD_CO_U32_e64:
9148+
case AMDGPU::V_ADD_CO_U32_e64_dpp:
9149+
case AMDGPU::V_ADD_CO_U32_sdwa:
9150+
//
9151+
case AMDGPU::V_ADD_U32_dpp:
9152+
case AMDGPU::V_ADD_U32_e32:
9153+
case AMDGPU::V_ADD_U32_e64:
9154+
case AMDGPU::V_ADD_U32_e64_dpp:
9155+
case AMDGPU::V_ADD_U32_sdwa:
9156+
//
9157+
case AMDGPU::V_DIV_FIXUP_F16_gfx9_e64:
9158+
case AMDGPU::V_FMA_F16_gfx9_e64:
9159+
case AMDGPU::V_INTERP_P2_F16:
9160+
case AMDGPU::V_MAD_F16_e64:
9161+
case AMDGPU::V_MAD_U16_e64:
9162+
case AMDGPU::V_MAD_I16_e64:
9163+
//
9164+
case AMDGPU::V_SUBBREV_U32_dpp:
9165+
case AMDGPU::V_SUBBREV_U32_e32:
9166+
case AMDGPU::V_SUBBREV_U32_e64:
9167+
case AMDGPU::V_SUBBREV_U32_e64_dpp:
9168+
case AMDGPU::V_SUBBREV_U32_sdwa:
9169+
//
9170+
case AMDGPU::V_SUBB_U32_dpp:
9171+
case AMDGPU::V_SUBB_U32_e32:
9172+
case AMDGPU::V_SUBB_U32_e64:
9173+
case AMDGPU::V_SUBB_U32_e64_dpp:
9174+
case AMDGPU::V_SUBB_U32_sdwa:
9175+
//
9176+
case AMDGPU::V_SUBREV_CO_U32_dpp:
9177+
case AMDGPU::V_SUBREV_CO_U32_e32:
9178+
case AMDGPU::V_SUBREV_CO_U32_e64:
9179+
case AMDGPU::V_SUBREV_CO_U32_e64_dpp:
9180+
case AMDGPU::V_SUBREV_CO_U32_sdwa:
9181+
//
9182+
case AMDGPU::V_SUBREV_U32_dpp:
9183+
case AMDGPU::V_SUBREV_U32_e32:
9184+
case AMDGPU::V_SUBREV_U32_e64:
9185+
case AMDGPU::V_SUBREV_U32_e64_dpp:
9186+
case AMDGPU::V_SUBREV_U32_sdwa:
9187+
//
9188+
case AMDGPU::V_SUB_CO_U32_dpp:
9189+
case AMDGPU::V_SUB_CO_U32_e32:
9190+
case AMDGPU::V_SUB_CO_U32_e64:
9191+
case AMDGPU::V_SUB_CO_U32_e64_dpp:
9192+
case AMDGPU::V_SUB_CO_U32_sdwa:
9193+
//
9194+
case AMDGPU::V_SUB_U32_dpp:
9195+
case AMDGPU::V_SUB_U32_e32:
9196+
case AMDGPU::V_SUB_U32_e64:
9197+
case AMDGPU::V_SUB_U32_e64_dpp:
9198+
case AMDGPU::V_SUB_U32_sdwa:
91999199
return true;
92009200
default:
92019201
return false;
@@ -9207,10 +9207,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
92079207

92089208
unsigned Gen = subtargetEncodingFamily(ST);
92099209

9210-
if (isRenamedInGFX9(Opcode) &&
9211-
ST.getGeneration() == AMDGPUSubtarget::GFX9){
9210+
if (isRenamedInGFX9(Opcode) && ST.getGeneration() == AMDGPUSubtarget::GFX9) {
92129211
Gen = SIEncodingFamily::GFX9;
9213-
}
9212+
}
92149213

92159214
// Adjust the encoding family to GFX80 for D16 buffer instructions when the
92169215
// subtarget has UnpackedD16VMem feature.

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1340,7 +1340,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
13401340
bool isAsmOnlyOpcode(int MCOp) const;
13411341

13421342
bool isRenamedInGFX9(int Opcode) const;
1343-
1343+
13441344
const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
13451345
const TargetRegisterInfo *TRI,
13461346
const MachineFunction &MF)

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