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[DAG] Don't split f64 constant stores if the fp imm is legal
If the target can generate a specific fp immediate constant, then don't split the store into 2 x i32 stores Another cleanup step for #74304
1 parent 7c85fcb commit a6da0b9

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11 files changed

+106
-110
lines changed

11 files changed

+106
-110
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20940,8 +20940,8 @@ SDValue DAGCombiner::replaceStoreOfFPConstant(StoreSDNode *ST) {
2094020940
Ptr, ST->getMemOperand());
2094120941
}
2094220942

20943-
if (ST->isSimple() &&
20944-
TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
20943+
if (ST->isSimple() && TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32) &&
20944+
!TLI.isFPImmLegal(CFP->getValueAPF(), MVT::f64)) {
2094520945
// Many FP stores are not made apparent until after legalize, e.g. for
2094620946
// argument passing. Since this is so common, custom legalize the
2094720947
// 64-bit integer store into two 32-bit stores.

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -461,7 +461,8 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
461461
ST->getOriginalAlign(), MMOFlags, AAInfo);
462462
}
463463

464-
if (CFP->getValueType(0) == MVT::f64) {
464+
if (CFP->getValueType(0) == MVT::f64 &&
465+
!TLI.isFPImmLegal(CFP->getValueAPF(), MVT::f64)) {
465466
// If this target supports 64-bit registers, do a single 64-bit store.
466467
if (TLI.isTypeLegal(MVT::i64)) {
467468
SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().

‎llvm/test/CodeGen/ARM/aapcs-hfa-code.ll

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -104,10 +104,8 @@ define arm_aapcs_vfpcc void @test_1double_nosplit([4 x float], [4 x double], [3
104104
; CHECK-NEXT: push {r11, lr}
105105
; CHECK-NEXT: .pad #8
106106
; CHECK-NEXT: sub sp, sp, #8
107-
; CHECK-NEXT: movw r1, #0
108-
; CHECK-NEXT: mov r0, #0
109-
; CHECK-NEXT: movt r1, #16368
110-
; CHECK-NEXT: strd r0, r1, [sp]
107+
; CHECK-NEXT: vmov.f64 d16, #1.000000e+00
108+
; CHECK-NEXT: vstr d16, [sp]
111109
; CHECK-NEXT: bl test_1double_nosplit
112110
; CHECK-NEXT: add sp, sp, #8
113111
; CHECK-NEXT: pop {r11, pc}
@@ -138,10 +136,8 @@ define arm_aapcs_vfpcc void @test_1double_misaligned([4 x double], [4 x double],
138136
; CHECK-NEXT: push {r11, lr}
139137
; CHECK-NEXT: .pad #16
140138
; CHECK-NEXT: sub sp, sp, #16
141-
; CHECK-NEXT: movw r1, #0
142-
; CHECK-NEXT: mov r0, #0
143-
; CHECK-NEXT: movt r1, #16368
144-
; CHECK-NEXT: strd r0, r1, [sp, #8]
139+
; CHECK-NEXT: vmov.f64 d16, #1.000000e+00
140+
; CHECK-NEXT: vstr d16, [sp, #8]
145141
; CHECK-NEXT: bl test_1double_misaligned
146142
; CHECK-NEXT: add sp, sp, #16
147143
; CHECK-NEXT: pop {r11, pc}

‎llvm/test/CodeGen/ARM/ha-alignstack-call.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -300,16 +300,16 @@ entry:
300300
ret double %call
301301
}
302302
; CHECK-LABEL: g2_1_call:
303-
; CHECK: movw r0, #0
304-
; CHECK: mov r1, #0
305-
; CHECK: movt r0, #16352
306-
; CHECK: str r1, [sp]
307-
; CHECK: stmib sp, {r0, r1}
308-
; CHECK: str r1, [sp, #12]
309-
; CHECK: str r1, [sp, #16]
310-
; CHECK: str r1, [sp, #20]
311-
; CHECK: str r1, [sp, #24]
312-
; CHECK: str r1, [sp, #28]
303+
; CHECK: vmov.f64 d16, #5.000000e-01
304+
; CHECK: mov r0, #0
305+
; CHECK: str r0, [sp, #8]
306+
; CHECK: str r0, [sp, #12]
307+
; CHECK: str r0, [sp, #16]
308+
; CHECK: vmov.i32 d0, #0x0
309+
; CHECK: str r0, [sp, #20]
310+
; CHECK: str r0, [sp, #24]
311+
; CHECK: str r0, [sp, #28]
312+
; CHECK: vstr d16, [sp]
313313
; CHECK: bl g2_1
314314

315315
; pass in memory, alignment 8

‎llvm/test/CodeGen/Mips/pr49200.ll

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -11,11 +11,10 @@ define dso_local void @foo() #0 {
1111
; CHECK-LABEL: foo:
1212
; CHECK: # %bb.0: # %entry
1313
; CHECK-NEXT: addiusp -24
14-
; CHECK-NEXT: li16 $2, 0
15-
; CHECK-NEXT: sw $2, 4($sp)
16-
; CHECK-NEXT: sw $2, 0($sp)
17-
; CHECK-NEXT: sw $2, 12($sp)
18-
; CHECK-NEXT: sw $2, 8($sp)
14+
; CHECK-NEXT: mtc1 $zero, $f0
15+
; CHECK-NEXT: mthc1 $zero, $f0
16+
; CHECK-NEXT: sdc1 $f0, 0($sp)
17+
; CHECK-NEXT: sdc1 $f0, 8($sp)
1918
; CHECK-NEXT: ldc1 $f0, 0($sp)
2019
; CHECK-NEXT: sdc1 $f0, 16($sp)
2120
; CHECK-NEXT: addiusp 24

‎llvm/test/CodeGen/X86/fp-intrinsics.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -865,9 +865,9 @@ define double @f19() #0 {
865865
; X87-NEXT: .cfi_def_cfa_offset 32
866866
; X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
867867
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
868+
; X87-NEXT: fld1
869+
; X87-NEXT: fstpl (%esp)
868870
; X87-NEXT: wait
869-
; X87-NEXT: movl $1072693248, {{[0-9]+}}(%esp) # imm = 0x3FF00000
870-
; X87-NEXT: movl $0, (%esp)
871871
; X87-NEXT: calll fmod
872872
; X87-NEXT: addl $28, %esp
873873
; X87-NEXT: .cfi_def_cfa_offset 4

‎llvm/test/CodeGen/X86/ldexp.ll

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -91,10 +91,11 @@ define double @ldexp_f64(i8 zeroext %x) {
9191
;
9292
; WIN32-LABEL: ldexp_f64:
9393
; WIN32: # %bb.0:
94+
; WIN32-NEXT: subl $12, %esp
9495
; WIN32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
95-
; WIN32-NEXT: pushl %eax
96-
; WIN32-NEXT: pushl $1072693248 # imm = 0x3FF00000
97-
; WIN32-NEXT: pushl $0
96+
; WIN32-NEXT: movl %eax, {{[0-9]+}}(%esp)
97+
; WIN32-NEXT: fld1
98+
; WIN32-NEXT: fstpl (%esp)
9899
; WIN32-NEXT: calll _ldexp
99100
; WIN32-NEXT: addl $12, %esp
100101
; WIN32-NEXT: retl

‎llvm/test/CodeGen/X86/memset64-on-x86-32.ll

Lines changed: 11 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -18,26 +18,17 @@ define void @bork(ptr nocapture align 4 %dst) nounwind {
1818
; SLOW_32-LABEL: bork:
1919
; SLOW_32: # %bb.0:
2020
; SLOW_32-NEXT: movl {{[0-9]+}}(%esp), %eax
21-
; SLOW_32-NEXT: movl $0, 4(%eax)
22-
; SLOW_32-NEXT: movl $0, (%eax)
23-
; SLOW_32-NEXT: movl $0, 12(%eax)
24-
; SLOW_32-NEXT: movl $0, 8(%eax)
25-
; SLOW_32-NEXT: movl $0, 20(%eax)
26-
; SLOW_32-NEXT: movl $0, 16(%eax)
27-
; SLOW_32-NEXT: movl $0, 28(%eax)
28-
; SLOW_32-NEXT: movl $0, 24(%eax)
29-
; SLOW_32-NEXT: movl $0, 36(%eax)
30-
; SLOW_32-NEXT: movl $0, 32(%eax)
31-
; SLOW_32-NEXT: movl $0, 44(%eax)
32-
; SLOW_32-NEXT: movl $0, 40(%eax)
33-
; SLOW_32-NEXT: movl $0, 52(%eax)
34-
; SLOW_32-NEXT: movl $0, 48(%eax)
35-
; SLOW_32-NEXT: movl $0, 60(%eax)
36-
; SLOW_32-NEXT: movl $0, 56(%eax)
37-
; SLOW_32-NEXT: movl $0, 68(%eax)
38-
; SLOW_32-NEXT: movl $0, 64(%eax)
39-
; SLOW_32-NEXT: movl $0, 76(%eax)
40-
; SLOW_32-NEXT: movl $0, 72(%eax)
21+
; SLOW_32-NEXT: xorps %xmm0, %xmm0
22+
; SLOW_32-NEXT: movsd %xmm0, 72(%eax)
23+
; SLOW_32-NEXT: movsd %xmm0, 64(%eax)
24+
; SLOW_32-NEXT: movsd %xmm0, 56(%eax)
25+
; SLOW_32-NEXT: movsd %xmm0, 48(%eax)
26+
; SLOW_32-NEXT: movsd %xmm0, 40(%eax)
27+
; SLOW_32-NEXT: movsd %xmm0, 32(%eax)
28+
; SLOW_32-NEXT: movsd %xmm0, 24(%eax)
29+
; SLOW_32-NEXT: movsd %xmm0, 16(%eax)
30+
; SLOW_32-NEXT: movsd %xmm0, 8(%eax)
31+
; SLOW_32-NEXT: movsd %xmm0, (%eax)
4132
; SLOW_32-NEXT: retl
4233
;
4334
; SLOW_64-LABEL: bork:

‎llvm/test/CodeGen/X86/pr38738.ll

Lines changed: 9 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -130,22 +130,15 @@ define void @tryset(ptr nocapture %x) {
130130
; X86SSE2-LABEL: tryset:
131131
; X86SSE2: # %bb.0:
132132
; X86SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
133-
; X86SSE2-NEXT: movl $0, 4(%eax)
134-
; X86SSE2-NEXT: movl $0, (%eax)
135-
; X86SSE2-NEXT: movl $0, 12(%eax)
136-
; X86SSE2-NEXT: movl $0, 8(%eax)
137-
; X86SSE2-NEXT: movl $0, 20(%eax)
138-
; X86SSE2-NEXT: movl $0, 16(%eax)
139-
; X86SSE2-NEXT: movl $0, 28(%eax)
140-
; X86SSE2-NEXT: movl $0, 24(%eax)
141-
; X86SSE2-NEXT: movl $0, 36(%eax)
142-
; X86SSE2-NEXT: movl $0, 32(%eax)
143-
; X86SSE2-NEXT: movl $0, 44(%eax)
144-
; X86SSE2-NEXT: movl $0, 40(%eax)
145-
; X86SSE2-NEXT: movl $0, 52(%eax)
146-
; X86SSE2-NEXT: movl $0, 48(%eax)
147-
; X86SSE2-NEXT: movl $0, 60(%eax)
148-
; X86SSE2-NEXT: movl $0, 56(%eax)
133+
; X86SSE2-NEXT: xorps %xmm0, %xmm0
134+
; X86SSE2-NEXT: movsd %xmm0, 56(%eax)
135+
; X86SSE2-NEXT: movsd %xmm0, 48(%eax)
136+
; X86SSE2-NEXT: movsd %xmm0, 40(%eax)
137+
; X86SSE2-NEXT: movsd %xmm0, 32(%eax)
138+
; X86SSE2-NEXT: movsd %xmm0, 24(%eax)
139+
; X86SSE2-NEXT: movsd %xmm0, 16(%eax)
140+
; X86SSE2-NEXT: movsd %xmm0, 8(%eax)
141+
; X86SSE2-NEXT: movsd %xmm0, (%eax)
149142
; X86SSE2-NEXT: retl
150143
;
151144
; X64AVX-LABEL: tryset:

‎llvm/test/CodeGen/X86/slow-unaligned-mem.ll

Lines changed: 54 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,16 @@
11
; Intel chips with slow unaligned memory accesses
22

3-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefixes=SLOW
4-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefixes=SLOW
5-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefixes=SLOW
6-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefixes=SLOW
7-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefixes=SLOW
8-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefixes=SLOW
9-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefixes=SLOW
10-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefixes=SLOW
11-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefixes=SLOW
12-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefixes=SLOW
13-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefixes=SLOW
3+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SCALAR
4+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SCALAR
5+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
6+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
7+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
8+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
9+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
10+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
11+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
12+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
13+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
1414

1515
; Intel chips with fast unaligned memory accesses
1616

@@ -26,15 +26,15 @@
2626

2727
; AMD chips with slow unaligned memory accesses
2828

29-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-4 2>&1 | FileCheck %s --check-prefixes=SLOW
30-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-xp 2>&1 | FileCheck %s --check-prefixes=SLOW
31-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=k8 2>&1 | FileCheck %s --check-prefixes=SLOW
32-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=opteron 2>&1 | FileCheck %s --check-prefixes=SLOW
33-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon64 2>&1 | FileCheck %s --check-prefixes=SLOW
34-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-fx 2>&1 | FileCheck %s --check-prefixes=SLOW
35-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=k8-sse3 2>&1 | FileCheck %s --check-prefixes=SLOW
36-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=opteron-sse3 2>&1 | FileCheck %s --check-prefixes=SLOW
37-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon64-sse3 2>&1 | FileCheck %s --check-prefixes=SLOW
29+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-4 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SCALAR
30+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-xp 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SCALAR
31+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=k8 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
32+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=opteron 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
33+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon64 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
34+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-fx 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
35+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=k8-sse3 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
36+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=opteron-sse3 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
37+
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon64-sse3 2>&1 | FileCheck %s --check-prefixes=SLOW,SLOW-SSE
3838

3939
; AMD chips with fast unaligned memory accesses
4040

@@ -67,26 +67,40 @@
6767
; SLOW-NOT: not a recognized processor
6868
; FAST-NOT: not a recognized processor
6969
define void @store_zeros(ptr %a) {
70-
; SLOW-LABEL: store_zeros:
71-
; SLOW: # %bb.0:
72-
; SLOW-NEXT: movl {{[0-9]+}}(%esp), %eax
73-
; SLOW-NEXT: movl $0
74-
; SLOW-NEXT: movl $0
75-
; SLOW-NEXT: movl $0
76-
; SLOW-NEXT: movl $0
77-
; SLOW-NEXT: movl $0
78-
; SLOW-NEXT: movl $0
79-
; SLOW-NEXT: movl $0
80-
; SLOW-NEXT: movl $0
81-
; SLOW-NEXT: movl $0
82-
; SLOW-NEXT: movl $0
83-
; SLOW-NEXT: movl $0
84-
; SLOW-NEXT: movl $0
85-
; SLOW-NEXT: movl $0
86-
; SLOW-NEXT: movl $0
87-
; SLOW-NEXT: movl $0
88-
; SLOW-NEXT: movl $0
89-
; SLOW-NOT: movl
70+
; SLOW-SCALAR-LABEL: store_zeros:
71+
; SLOW-SCALAR: # %bb.0:
72+
; SLOW-SCALAR-NEXT: movl {{[0-9]+}}(%esp), %eax
73+
; SLOW-SCALAR-NEXT: movl $0
74+
; SLOW-SCALAR-NEXT: movl $0
75+
; SLOW-SCALAR-NEXT: movl $0
76+
; SLOW-SCALAR-NEXT: movl $0
77+
; SLOW-SCALAR-NEXT: movl $0
78+
; SLOW-SCALAR-NEXT: movl $0
79+
; SLOW-SCALAR-NEXT: movl $0
80+
; SLOW-SCALAR-NEXT: movl $0
81+
; SLOW-SCALAR-NEXT: movl $0
82+
; SLOW-SCALAR-NEXT: movl $0
83+
; SLOW-SCALAR-NEXT: movl $0
84+
; SLOW-SCALAR-NEXT: movl $0
85+
; SLOW-SCALAR-NEXT: movl $0
86+
; SLOW-SCALAR-NEXT: movl $0
87+
; SLOW-SCALAR-NEXT: movl $0
88+
; SLOW-SCALAR-NEXT: movl $0
89+
; SLOW-SCALAR-NOT: movl
90+
;
91+
; SLOW-SSE-LABEL: store_zeros:
92+
; SLOW-SSE: # %bb.0:
93+
; SLOW-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
94+
; SLOW-SSE-NEXT: xorps %xmm0, %xmm0
95+
; SLOW-SSE-NEXT: movsd %xmm0
96+
; SLOW-SSE-NEXT: movsd %xmm0
97+
; SLOW-SSE-NEXT: movsd %xmm0
98+
; SLOW-SSE-NEXT: movsd %xmm0
99+
; SLOW-SSE-NEXT: movsd %xmm0
100+
; SLOW-SSE-NEXT: movsd %xmm0
101+
; SLOW-SSE-NEXT: movsd %xmm0
102+
; SLOW-SSE-NEXT: movsd %xmm0
103+
; SLOW-SSE-NOT: movsd
90104
;
91105
; FAST-SSE-LABEL: store_zeros:
92106
; FAST-SSE: # %bb.0:

‎llvm/test/CodeGen/X86/zero-remat.ll

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,11 +19,12 @@ define double @foo() nounwind {
1919
;
2020
; CHECK-32-LABEL: foo:
2121
; CHECK-32: # %bb.0:
22-
; CHECK-32-NEXT: pushl $0
23-
; CHECK-32-NEXT: pushl $0
22+
; CHECK-32-NEXT: subl $8, %esp
23+
; CHECK-32-NEXT: fldz
24+
; CHECK-32-NEXT: fstpl (%esp)
2425
; CHECK-32-NEXT: calll bar@PLT
25-
; CHECK-32-NEXT: addl $8, %esp
2626
; CHECK-32-NEXT: fldz
27+
; CHECK-32-NEXT: addl $8, %esp
2728
; CHECK-32-NEXT: retl
2829
call void @bar(double 0.0)
2930
ret double 0.0

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