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[RISCV] Use integer VTypeInfo predicate for vmv_v_v_vl pattern (#114915)
When lowering fixed length f16 insert_subvector nodes at index 0 we crashed with zvfhmin because we couldn't select vmv_v_v_vl. This was due to the predicates requiring full zvfh, even though we only need zve32x. Use the integer VTypeInfo instead similarly to VPatSlideVL_VX_VI. The extract_subvector tests aren't related but were just added for consistency with the insert_subvector tests.
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2305,7 +2305,8 @@ foreach vti = AllIntegerVectors in {
23052305

23062306
// 11.16. Vector Integer Move Instructions
23072307
foreach vti = AllVectors in {
2308-
let Predicates = GetVTypePredicates<vti>.Predicates in {
2308+
defvar ivti = GetIntVTypeInfo<vti>.Vti;
2309+
let Predicates = GetVTypePredicates<ivti>.Predicates in {
23092310
def : Pat<(vti.Vector (riscv_vmv_v_v_vl vti.RegClass:$passthru,
23102311
vti.RegClass:$rs2, VLOpFrag)),
23112312
(!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

Lines changed: 72 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,18 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
3-
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
2+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
3+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
4+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
5+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
46

5-
; RUN: llc -mtriple=riscv32 -mattr=+m,+v -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
6-
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
7+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
8+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
9+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
10+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
711

8-
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
9-
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
12+
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
13+
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
14+
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
15+
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
1016

1117
define void @extract_v2i8_v4i8_0(ptr %x, ptr %y) {
1218
; CHECK-LABEL: extract_v2i8_v4i8_0:
@@ -866,6 +872,66 @@ define <1 x i64> @extract_v1i64_v2i64_1(<2 x i64> %x) {
866872
ret <1 x i64> %v
867873
}
868874

875+
define void @extract_v2bf16_v4bf16_0(ptr %x, ptr %y) {
876+
; CHECK-LABEL: extract_v2bf16_v4bf16_0:
877+
; CHECK: # %bb.0:
878+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
879+
; CHECK-NEXT: vle16.v v8, (a0)
880+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
881+
; CHECK-NEXT: vse16.v v8, (a1)
882+
; CHECK-NEXT: ret
883+
%a = load <4 x bfloat>, ptr %x
884+
%c = call <2 x bfloat> @llvm.vector.extract.v2bf16.v4bf16(<4 x bfloat> %a, i64 0)
885+
store <2 x bfloat> %c, ptr %y
886+
ret void
887+
}
888+
889+
define void @extract_v2bf16_v4bf16_2(ptr %x, ptr %y) {
890+
; CHECK-LABEL: extract_v2bf16_v4bf16_2:
891+
; CHECK: # %bb.0:
892+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
893+
; CHECK-NEXT: vle16.v v8, (a0)
894+
; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
895+
; CHECK-NEXT: vslidedown.vi v8, v8, 2
896+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
897+
; CHECK-NEXT: vse16.v v8, (a1)
898+
; CHECK-NEXT: ret
899+
%a = load <4 x bfloat>, ptr %x
900+
%c = call <2 x bfloat> @llvm.vector.extract.v2bf16.v4bf16(<4 x bfloat> %a, i64 2)
901+
store <2 x bfloat> %c, ptr %y
902+
ret void
903+
}
904+
905+
define void @extract_v2f16_v4f16_0(ptr %x, ptr %y) {
906+
; CHECK-LABEL: extract_v2f16_v4f16_0:
907+
; CHECK: # %bb.0:
908+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
909+
; CHECK-NEXT: vle16.v v8, (a0)
910+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
911+
; CHECK-NEXT: vse16.v v8, (a1)
912+
; CHECK-NEXT: ret
913+
%a = load <4 x half>, ptr %x
914+
%c = call <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half> %a, i64 0)
915+
store <2 x half> %c, ptr %y
916+
ret void
917+
}
918+
919+
define void @extract_v2f16_v4f16_2(ptr %x, ptr %y) {
920+
; CHECK-LABEL: extract_v2f16_v4f16_2:
921+
; CHECK: # %bb.0:
922+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
923+
; CHECK-NEXT: vle16.v v8, (a0)
924+
; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
925+
; CHECK-NEXT: vslidedown.vi v8, v8, 2
926+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
927+
; CHECK-NEXT: vse16.v v8, (a1)
928+
; CHECK-NEXT: ret
929+
%a = load <4 x half>, ptr %x
930+
%c = call <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half> %a, i64 2)
931+
store <2 x half> %c, ptr %y
932+
ret void
933+
}
934+
869935
declare <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %vec, i64 %idx)
870936
declare <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %vec, i64 %idx)
871937

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

Lines changed: 96 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,18 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV32VLA
3-
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV64VLA
2+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV32VLA
3+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV64VLA
4+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV32VLA
5+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV64VLA
46

5-
; RUN: llc -mtriple=riscv32 -mattr=+m,+v -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV32VLA
6-
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV64VLA
7+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV32VLA
8+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV64VLA
9+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV32VLA
10+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV64VLA
711

8-
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS,RV32VLS %s
9-
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS,RV64VLS %s
12+
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS,RV32VLS %s
13+
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS,RV64VLS %s
14+
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS,RV32VLS %s
15+
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS,RV64VLS %s
1016

1117
define <vscale x 8 x i32> @insert_nxv8i32_v2i32_0(<vscale x 8 x i32> %vec, ptr %svp) {
1218
; VLA-LABEL: insert_nxv8i32_v2i32_0:
@@ -860,6 +866,90 @@ define void @insert_v2i64_nxv16i64_hi(ptr %psv, ptr %out) {
860866
ret void
861867
}
862868

869+
define <vscale x 8 x bfloat> @insert_nxv8bf16_v2bf16_0(<vscale x 8 x bfloat> %vec, ptr %svp) {
870+
; VLA-LABEL: insert_nxv8bf16_v2bf16_0:
871+
; VLA: # %bb.0:
872+
; VLA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
873+
; VLA-NEXT: vle16.v v10, (a0)
874+
; VLA-NEXT: vsetivli zero, 2, e16, m2, tu, ma
875+
; VLA-NEXT: vmv.v.v v8, v10
876+
; VLA-NEXT: ret
877+
;
878+
; VLS-LABEL: insert_nxv8bf16_v2bf16_0:
879+
; VLS: # %bb.0:
880+
; VLS-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
881+
; VLS-NEXT: vle16.v v10, (a0)
882+
; VLS-NEXT: vsetivli zero, 2, e16, m1, tu, ma
883+
; VLS-NEXT: vmv.v.v v8, v10
884+
; VLS-NEXT: ret
885+
%sv = load <2 x bfloat>, ptr %svp
886+
%v = call <vscale x 8 x bfloat> @llvm.vector.insert.v2bf16.nxv8bf16(<vscale x 8 x bfloat> %vec, <2 x bfloat> %sv, i64 0)
887+
ret <vscale x 8 x bfloat> %v
888+
}
889+
890+
define <vscale x 8 x bfloat> @insert_nxv8bf16_v2bf16_2(<vscale x 8 x bfloat> %vec, ptr %svp) {
891+
; VLA-LABEL: insert_nxv8bf16_v2bf16_2:
892+
; VLA: # %bb.0:
893+
; VLA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
894+
; VLA-NEXT: vle16.v v10, (a0)
895+
; VLA-NEXT: vsetivli zero, 4, e16, m2, tu, ma
896+
; VLA-NEXT: vslideup.vi v8, v10, 2
897+
; VLA-NEXT: ret
898+
;
899+
; VLS-LABEL: insert_nxv8bf16_v2bf16_2:
900+
; VLS: # %bb.0:
901+
; VLS-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
902+
; VLS-NEXT: vle16.v v10, (a0)
903+
; VLS-NEXT: vsetivli zero, 4, e16, m1, tu, ma
904+
; VLS-NEXT: vslideup.vi v8, v10, 2
905+
; VLS-NEXT: ret
906+
%sv = load <2 x bfloat>, ptr %svp
907+
%v = call <vscale x 8 x bfloat> @llvm.vector.insert.v2bf16.nxv8bf16(<vscale x 8 x bfloat> %vec, <2 x bfloat> %sv, i64 2)
908+
ret <vscale x 8 x bfloat> %v
909+
}
910+
911+
define <vscale x 8 x half> @insert_nxv8f16_v2f16_0(<vscale x 8 x half> %vec, ptr %svp) {
912+
; VLA-LABEL: insert_nxv8f16_v2f16_0:
913+
; VLA: # %bb.0:
914+
; VLA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
915+
; VLA-NEXT: vle16.v v10, (a0)
916+
; VLA-NEXT: vsetivli zero, 2, e16, m2, tu, ma
917+
; VLA-NEXT: vmv.v.v v8, v10
918+
; VLA-NEXT: ret
919+
;
920+
; VLS-LABEL: insert_nxv8f16_v2f16_0:
921+
; VLS: # %bb.0:
922+
; VLS-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
923+
; VLS-NEXT: vle16.v v10, (a0)
924+
; VLS-NEXT: vsetivli zero, 2, e16, m1, tu, ma
925+
; VLS-NEXT: vmv.v.v v8, v10
926+
; VLS-NEXT: ret
927+
%sv = load <2 x half>, ptr %svp
928+
%v = call <vscale x 8 x half> @llvm.vector.insert.v2f16.nxv8f16(<vscale x 8 x half> %vec, <2 x half> %sv, i64 0)
929+
ret <vscale x 8 x half> %v
930+
}
931+
932+
define <vscale x 8 x half> @insert_nxv8f16_v2f16_2(<vscale x 8 x half> %vec, ptr %svp) {
933+
; VLA-LABEL: insert_nxv8f16_v2f16_2:
934+
; VLA: # %bb.0:
935+
; VLA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
936+
; VLA-NEXT: vle16.v v10, (a0)
937+
; VLA-NEXT: vsetivli zero, 4, e16, m2, tu, ma
938+
; VLA-NEXT: vslideup.vi v8, v10, 2
939+
; VLA-NEXT: ret
940+
;
941+
; VLS-LABEL: insert_nxv8f16_v2f16_2:
942+
; VLS: # %bb.0:
943+
; VLS-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
944+
; VLS-NEXT: vle16.v v10, (a0)
945+
; VLS-NEXT: vsetivli zero, 4, e16, m1, tu, ma
946+
; VLS-NEXT: vslideup.vi v8, v10, 2
947+
; VLS-NEXT: ret
948+
%sv = load <2 x half>, ptr %svp
949+
%v = call <vscale x 8 x half> @llvm.vector.insert.v2f16.nxv8f16(<vscale x 8 x half> %vec, <2 x half> %sv, i64 2)
950+
ret <vscale x 8 x half> %v
951+
}
952+
863953
declare <8 x i1> @llvm.vector.insert.v4i1.v8i1(<8 x i1>, <4 x i1>, i64)
864954
declare <32 x i1> @llvm.vector.insert.v8i1.v32i1(<32 x i1>, <8 x i1>, i64)
865955

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