Skip to content

Commit a7f3c0a

Browse files
4vtomat4vtomat
committed
fixup! [llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention
1 parent 688206b commit a7f3c0a

File tree

3 files changed

+34
-25
lines changed

3 files changed

+34
-25
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -362,17 +362,17 @@ void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, unsigned NF, bool IsMasked,
362362
/*IsStridedOrIndexed*/ true, Operands,
363363
/*IsLoad=*/true, &IndexVT);
364364

365+
#ifndef NDEBUG
365366
// Number of element = RVVBitsPerBlock * LMUL / SEW
366367
unsigned ContainedTyNumElts = RISCV::RVVBitsPerBlock >> Log2SEW;
367-
unsigned Log2LMUL = static_cast<unsigned>(LMUL);
368-
if (Log2LMUL > 3) {
369-
Log2LMUL = 8 - Log2LMUL;
370-
ContainedTyNumElts = ContainedTyNumElts >> Log2LMUL;
371-
} else {
372-
ContainedTyNumElts = ContainedTyNumElts << Log2LMUL;
373-
}
368+
auto DecodedLMUL = RISCVVType::decodeVLMUL(LMUL);
369+
if (DecodedLMUL.second)
370+
ContainedTyNumElts /= DecodedLMUL.first;
371+
else
372+
ContainedTyNumElts *= DecodedLMUL.first;
374373
assert(ContainedTyNumElts == IndexVT.getVectorMinNumElements() &&
375374
"Element count mismatch");
375+
#endif
376376

377377
RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
378378
unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
@@ -437,17 +437,17 @@ void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, unsigned NF, bool IsMasked,
437437
/*IsStridedOrIndexed*/ true, Operands,
438438
/*IsLoad=*/false, &IndexVT);
439439

440+
#ifndef NDEBUG
440441
// Number of element = RVVBitsPerBlock * LMUL / SEW
441442
unsigned ContainedTyNumElts = RISCV::RVVBitsPerBlock >> Log2SEW;
442-
unsigned Log2LMUL = static_cast<unsigned>(LMUL);
443-
if (Log2LMUL > 3) {
444-
Log2LMUL = 8 - Log2LMUL;
445-
ContainedTyNumElts = ContainedTyNumElts >> Log2LMUL;
446-
} else {
447-
ContainedTyNumElts = ContainedTyNumElts << Log2LMUL;
448-
}
443+
auto DecodedLMUL = RISCVVType::decodeVLMUL(LMUL);
444+
if (DecodedLMUL.second)
445+
ContainedTyNumElts /= DecodedLMUL.first;
446+
else
447+
ContainedTyNumElts *= DecodedLMUL.first;
449448
assert(ContainedTyNumElts == IndexVT.getVectorMinNumElements() &&
450449
"Element count mismatch");
450+
#endif
451451

452452
RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
453453
unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -6908,8 +6908,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
69086908
EVT VecTy = Load->getMemoryVT();
69096909
// Handle normal vector tuple load.
69106910
if (VecTy.isRISCVVectorTuple()) {
6911-
MachineFunction &MF = DAG.getMachineFunction();
6912-
MachineFrameInfo &MFI = MF.getFrameInfo();
69136911
SDLoc DL(Op);
69146912
MVT XLenVT = Subtarget.getXLenVT();
69156913
unsigned NF = VecTy.getRISCVVectorTupleNumFields();
@@ -6921,23 +6919,24 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
69216919
Flag.setNoUnsignedWrap(true);
69226920
SDValue Ret = DAG.getUNDEF(VecTy);
69236921
SDValue BasePtr = Load->getBasePtr();
6924-
if (auto *FI = dyn_cast<FrameIndexSDNode>(BasePtr))
6925-
MFI.setStackID(FI->getIndex(), TargetStackID::ScalableVector);
69266922
SDValue VROffset = DAG.getNode(RISCVISD::READ_VLENB, DL, XLenVT);
69276923
VROffset =
69286924
DAG.getNode(ISD::SHL, DL, XLenVT, VROffset,
69296925
DAG.getConstant(std::max(Log2LMUL, 0), DL, XLenVT));
6926+
SmallVector<SDValue, 8> OutChains;
69306927

69316928
// Load NF vector registers and combine them to a vector tuple.
69326929
for (unsigned i = 0; i < NF; ++i) {
69336930
SDValue LoadVal = DAG.getLoad(
6934-
MVT::getScalableVectorVT(MVT::i8, NumElts), DL, DAG.getEntryNode(),
6931+
MVT::getScalableVectorVT(MVT::i8, NumElts), DL, Load->getChain(),
69356932
BasePtr, MachinePointerInfo(Load->getAddressSpace()), Align(8));
6933+
OutChains.push_back(LoadVal.getValue(1));
69366934
Ret = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, VecTy, Ret, LoadVal,
69376935
DAG.getVectorIdxConstant(i, DL));
69386936
BasePtr = DAG.getNode(ISD::ADD, DL, XLenVT, BasePtr, VROffset, Flag);
69396937
}
6940-
return DAG.getMergeValues({Ret, DAG.getEntryNode()}, DL);
6938+
return DAG.getMergeValues(
6939+
{Ret, DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains)}, DL);
69416940
}
69426941

69436942
if (auto V = expandUnalignedRVVLoad(Op, DAG))
@@ -6952,8 +6951,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
69526951
EVT VecTy = StoredVal.getValueType();
69536952
// Handle normal vector tuple store.
69546953
if (VecTy.isRISCVVectorTuple()) {
6955-
MachineFunction &MF = DAG.getMachineFunction();
6956-
MachineFrameInfo &MFI = MF.getFrameInfo();
69576954
SDLoc DL(Op);
69586955
MVT XLenVT = Subtarget.getXLenVT();
69596956
unsigned NF = VecTy.getRISCVVectorTupleNumFields();
@@ -6966,8 +6963,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
69666963
SDValue Ret;
69676964
SDValue Chain = Store->getChain();
69686965
SDValue BasePtr = Store->getBasePtr();
6969-
if (auto *FI = dyn_cast<FrameIndexSDNode>(BasePtr))
6970-
MFI.setStackID(FI->getIndex(), TargetStackID::ScalableVector);
69716966
SDValue VROffset = DAG.getNode(RISCVISD::READ_VLENB, DL, XLenVT);
69726967
VROffset =
69736968
DAG.getNode(ISD::SHL, DL, XLenVT, VROffset,

‎llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,18 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
1111
; CHECK-NEXT: vmv.v.i v10, 0
12-
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
1312
; CHECK-NEXT: csrr a0, vlenb
1413
; CHECK-NEXT: srli a0, a0, 2
1514
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
1615
; CHECK-NEXT: vslidedown.vx v8, v0, a0
1716
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
17+
; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
18+
; CHECK-NEXT: vmv1r.v v0, v8
19+
; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
20+
; CHECK-NEXT: vnsrl.wi v8, v12, 0
21+
; CHECK-NEXT: vmsne.vi v0, v8, 0
22+
; CHECK-NEXT: vnsrl.wi v10, v12, 8
23+
; CHECK-NEXT: vmsne.vi v8, v10, 0
1824
; CHECK-NEXT: ret
1925
%retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec)
2026
ret {<vscale x 16 x i1>, <vscale x 16 x i1>} %retval
@@ -105,10 +111,18 @@ define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv
105111
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
106112
; CHECK-NEXT: vnsrl.wi v12, v24, 0
107113
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
114+
; CHECK-NEXT: vmsne.vi v0, v8, 0
115+
; CHECK-NEXT: addi a0, sp, 16
116+
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
108117
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
109118
; CHECK-NEXT: vnsrl.wi v16, v8, 8
110119
; CHECK-NEXT: vnsrl.wi v20, v24, 8
111120
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
121+
; CHECK-NEXT: vmsne.vi v8, v16, 0
122+
; CHECK-NEXT: csrr a0, vlenb
123+
; CHECK-NEXT: slli a0, a0, 3
124+
; CHECK-NEXT: add sp, sp, a0
125+
; CHECK-NEXT: addi sp, sp, 16
112126
; CHECK-NEXT: ret
113127
%retval = call {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.vector.deinterleave2.nxv128i1(<vscale x 128 x i1> %vec)
114128
ret {<vscale x 64 x i1>, <vscale x 64 x i1>} %retval

0 commit comments

Comments
 (0)