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Fix llvm-mca not to consider artificial subregs
1 parent c96fbce commit a82ac46

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5 files changed

+277
-264
lines changed

5 files changed

+277
-264
lines changed

llvm/include/llvm/MC/MCRegisterInfo.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,9 @@ struct MCRegisterDesc {
129129

130130
// Is true for constant registers.
131131
bool IsConstant;
132+
133+
// Is true for artificial registers.
134+
bool IsArtificial;
132135
};
133136

134137
/// MCRegisterInfo base class - We assume that the target defines a static
@@ -396,6 +399,9 @@ class MCRegisterInfo {
396399
/// Returns true if the given register is constant.
397400
bool isConstant(MCRegister RegNo) const { return get(RegNo).IsConstant; }
398401

402+
/// Returns true if the given register is artificial.
403+
bool isArtificial(MCRegister RegNo) const { return get(RegNo).IsArtificial; }
404+
399405
/// Return the number of registers this target has (useful for
400406
/// sizing arrays holding per register information)
401407
unsigned getNumRegs() const {

llvm/lib/MCA/HardwareUnits/RegisterFile.cpp

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,11 @@ namespace mca {
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2525
const unsigned WriteRef::INVALID_IID = std::numeric_limits<unsigned>::max();
2626

27+
static std::function<bool(MCPhysReg)>
28+
isNonArtificial(const MCRegisterInfo &MRI) {
29+
return [&MRI](MCPhysReg R) { return !MRI.isArtificial(R); };
30+
}
31+
2732
WriteRef::WriteRef(unsigned SourceIndex, WriteState *WS)
2833
: IID(SourceIndex), WriteBackCycle(), WriteResID(), RegisterID(),
2934
Write(WS) {}
@@ -282,7 +287,8 @@ void RegisterFile::addRegisterWrite(WriteRef Write,
282287
MCPhysReg ZeroRegisterID =
283288
WS.clearsSuperRegisters() ? RegID : WS.getRegisterID();
284289
ZeroRegisters.setBitVal(ZeroRegisterID, IsWriteZero);
285-
for (MCPhysReg I : MRI.subregs(ZeroRegisterID))
290+
for (MCPhysReg I :
291+
make_filter_range(MRI.subregs(ZeroRegisterID), isNonArtificial(MRI)))
286292
ZeroRegisters.setBitVal(I, IsWriteZero);
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288294
// If this move has been eliminated, then method tryEliminateMoveOrSwap should
@@ -304,7 +310,8 @@ void RegisterFile::addRegisterWrite(WriteRef Write,
304310
// Update the mapping for register RegID including its sub-registers.
305311
RegisterMappings[RegID].first = Write;
306312
RegisterMappings[RegID].second.AliasRegID = 0U;
307-
for (MCPhysReg I : MRI.subregs(RegID)) {
313+
for (MCPhysReg I :
314+
make_filter_range(MRI.subregs(RegID), isNonArtificial(MRI))) {
308315
RegisterMappings[I].first = Write;
309316
RegisterMappings[I].second.AliasRegID = 0U;
310317
}
@@ -472,7 +479,8 @@ bool RegisterFile::tryEliminateMoveOrSwap(MutableArrayRef<WriteState> Writes,
472479
AliasedReg = RMAlias.AliasRegID;
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474481
RegisterMappings[AliasReg].second.AliasRegID = AliasedReg;
475-
for (MCPhysReg I : MRI.subregs(AliasReg))
482+
for (MCPhysReg I :
483+
make_filter_range(MRI.subregs(AliasReg), isNonArtificial(MRI)))
476484
RegisterMappings[I].second.AliasRegID = AliasedReg;
477485

478486
if (ZeroRegisters[RS.getRegisterID()]) {

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