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sjoerdmeijersjoerdmeijer
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[AArch64] Set MaxInterleaving to 4 for Neoverse V2
1 parent acfa8a0 commit a834320

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13 files changed

+172
-5
lines changed

13 files changed

+172
-5
lines changed

‎llvm/include/llvm/Analysis/TargetTransformInfo.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -626,6 +626,10 @@ class TargetTransformInfo {
626626
AssumptionCache &AC, TargetLibraryInfo *LibInfo,
627627
HardwareLoopInfo &HWLoopInfo) const;
628628

629+
// Query the target for which minimum vectorization factor epilogue
630+
// vectorization should be considered.
631+
unsigned getEpilogueVectorizationMinVF() const;
632+
629633
/// Query the target whether it would be prefered to create a predicated
630634
/// vector loop, which can avoid the need to emit a scalar epilogue loop.
631635
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const;
@@ -1865,6 +1869,7 @@ class TargetTransformInfo::Concept {
18651869
AssumptionCache &AC,
18661870
TargetLibraryInfo *LibInfo,
18671871
HardwareLoopInfo &HWLoopInfo) = 0;
1872+
virtual unsigned getEpilogueVectorizationMinVF() = 0;
18681873
virtual bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) = 0;
18691874
virtual TailFoldingStyle
18701875
getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) = 0;
@@ -2319,6 +2324,9 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
23192324
HardwareLoopInfo &HWLoopInfo) override {
23202325
return Impl.isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
23212326
}
2327+
unsigned getEpilogueVectorizationMinVF() override {
2328+
return Impl.getEpilogueVectorizationMinVF();
2329+
}
23222330
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) override {
23232331
return Impl.preferPredicateOverEpilogue(TFI);
23242332
}

‎llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -192,6 +192,8 @@ class TargetTransformInfoImplBase {
192192
return false;
193193
}
194194

195+
unsigned getEpilogueVectorizationMinVF() const { return 16; }
196+
195197
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const { return false; }
196198

197199
TailFoldingStyle

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -667,6 +667,10 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
667667
return BaseT::isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
668668
}
669669

670+
unsigned getEpilogueVectorizationMinVF() {
671+
return BaseT::getEpilogueVectorizationMinVF();
672+
}
673+
670674
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) {
671675
return BaseT::preferPredicateOverEpilogue(TFI);
672676
}

‎llvm/lib/Analysis/TargetTransformInfo.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -352,6 +352,10 @@ bool TargetTransformInfo::isHardwareLoopProfitable(
352352
return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
353353
}
354354

355+
unsigned TargetTransformInfo::getEpilogueVectorizationMinVF() const {
356+
return TTIImpl->getEpilogueVectorizationMinVF();
357+
}
358+
355359
bool TargetTransformInfo::preferPredicateOverEpilogue(
356360
TailFoldingInfo *TFI) const {
357361
return TTIImpl->preferPredicateOverEpilogue(TFI);

‎llvm/lib/Target/AArch64/AArch64Subtarget.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -234,12 +234,13 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
234234
MaxBytesForLoopAlignment = 16;
235235
break;
236236
case NeoverseV2:
237-
// Specialize cost for Neoverse-V2.
237+
case NeoverseV3:
238+
EpilogueVectorizationMinVF = 8;
239+
MaxInterleaveFactor = 4;
238240
ScatterOverhead = 13;
239241
LLVM_FALLTHROUGH;
240242
case NeoverseN2:
241243
case NeoverseN3:
242-
case NeoverseV3:
243244
PrefFunctionAlignment = Align(16);
244245
PrefLoopAlignment = Align(32);
245246
MaxBytesForLoopAlignment = 16;

‎llvm/lib/Target/AArch64/AArch64Subtarget.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
5656
bool ATTRIBUTE = DEFAULT;
5757
#include "AArch64GenSubtargetInfo.inc"
5858

59+
unsigned EpilogueVectorizationMinVF = 16;
5960
uint8_t MaxInterleaveFactor = 2;
6061
uint8_t VectorInsertExtractBaseCost = 2;
6162
uint16_t CacheLineSize = 0;
@@ -225,6 +226,9 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
225226
hasFuseAdrpAdd() || hasFuseLiterals();
226227
}
227228

229+
unsigned getEpilogueVectorizationMinVF() const {
230+
return EpilogueVectorizationMinVF;
231+
}
228232
unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
229233
unsigned getVectorInsertExtractBaseCost() const;
230234
unsigned getCacheLineSize() const override { return CacheLineSize; }

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4581,6 +4581,10 @@ static bool containsDecreasingPointers(Loop *TheLoop,
45814581
return false;
45824582
}
45834583

4584+
unsigned AArch64TTIImpl::getEpilogueVectorizationMinVF() const {
4585+
return ST->getEpilogueVectorizationMinVF();
4586+
}
4587+
45844588
bool AArch64TTIImpl::preferPredicateOverEpilogue(TailFoldingInfo *TFI) {
45854589
if (!ST->hasSVE())
45864590
return false;

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -376,6 +376,8 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
376376
return ST->useFixedOverScalableIfEqualCost();
377377
}
378378

379+
unsigned getEpilogueVectorizationMinVF() const;
380+
379381
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI);
380382

381383
bool supportsScalableVectors() const {

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -185,7 +185,7 @@ static cl::opt<unsigned> EpilogueVectorizationForceVF(
185185
"loops."));
186186

187187
static cl::opt<unsigned> EpilogueVectorizationMinVF(
188-
"epilogue-vectorization-minimum-VF", cl::init(16), cl::Hidden,
188+
"epilogue-vectorization-minimum-VF", cl::Hidden,
189189
cl::desc("Only loops with vectorization factor equal to or larger than "
190190
"the specified value are considered for epilogue vectorization."));
191191

@@ -4644,7 +4644,11 @@ bool LoopVectorizationCostModel::isEpilogueVectorizationProfitable(
46444644
if (TTI.getMaxInterleaveFactor(VF) <= 1)
46454645
return false;
46464646

4647-
if ((Multiplier * VF.getKnownMinValue()) >= EpilogueVectorizationMinVF)
4647+
unsigned MinVFThreshold = EpilogueVectorizationMinVF.getNumOccurrences() > 0
4648+
? EpilogueVectorizationMinVF
4649+
: TTI.getEpilogueVectorizationMinVF();
4650+
4651+
if ((Multiplier * VF.getKnownMinValue()) >= MinVFThreshold)
46484652
return true;
46494653
return false;
46504654
}

‎llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@
55
; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macos -mcpu=apple-a14 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
66
; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macos -mcpu=apple-a15 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
77
; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macos -mcpu=apple-a16 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
8+
; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v2 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
9+
; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v3 -S %s | FileCheck --check-prefix=INTERLEAVE-4-VLA %s
810

911
; Tests for selecting interleave counts for loops with loads and stores.
1012

@@ -213,6 +215,12 @@ define void @interleave_single_load_store(ptr %src, ptr %dst, i64 %N, i8 %a, i8
213215
; INTERLEAVE-2: exit:
214216
; INTERLEAVE-2-NEXT: ret void
215217
;
218+
; INTERLEAVE-4-VLA-LABEL: @interleave_single_load_store(
219+
; INTERLEAVE-4-VLA: call <vscale x 16 x i8> @llvm.smax.nxv16i8(
220+
; INTERLEAVE-4-VLA-NEXT: call <vscale x 16 x i8> @llvm.smax.nxv16i8(
221+
; INTERLEAVE-4-VLA-NEXT: call <vscale x 16 x i8> @llvm.smax.nxv16i8(
222+
; INTERLEAVE-4-VLA-NEXT: call <vscale x 16 x i8> @llvm.smax.nxv16i8(
223+
;
216224
entry:
217225
br label %loop
218226

‎llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@
55
; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macos -mcpu=apple-a14 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
66
; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macos -mcpu=apple-a15 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
77
; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macos -mcpu=apple-a16 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
8+
; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v2 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
9+
; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v3 -S %s | FileCheck --check-prefix=INTERLEAVE-4-VLA %s
810

911
; Tests for selecting the interleave count for loops with reductions.
1012

@@ -138,6 +140,12 @@ define i32 @interleave_integer_reduction(ptr %src, i64 %N) {
138140
; INTERLEAVE-2-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i32 [ [[RED_NEXT]], [[LOOP]] ], [ [[TMP9]], [[MIDDLE_BLOCK]] ]
139141
; INTERLEAVE-2-NEXT: ret i32 [[RED_NEXT_LCSSA]]
140142
;
143+
; INTERLEAVE-4-VLA-LABEL: @interleave_integer_reduction(
144+
; INTERLEAVE-4-VLA: add <vscale x 4 x i32>
145+
; INTERLEAVE-4-VLA-NEXT: add <vscale x 4 x i32>
146+
; INTERLEAVE-4-VLA-NEXT: add <vscale x 4 x i32>
147+
; INTERLEAVE-4-VLA-NEXT: add <vscale x 4 x i32>
148+
;
141149
entry:
142150
br label %loop
143151

‎llvm/test/Transforms/LoopVectorize/AArch64/neoverse-epilogue-vect.ll

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
1+
; RUN: opt -passes=loop-vectorize -S < %s | FileCheck %s
2+
3+
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
4+
target triple = "aarch64-unknown-linux-gnu"
5+
6+
define noundef i32 @V1(ptr noalias nocapture noundef %0, ptr noalias nocapture noundef readonly %1, i32 noundef %2) #0 {
7+
; CHECK-LABEL: @V1(
8+
; CHECK-NOT: vec.epilog.ph:
9+
; CHECK-NOT: vec.epilog.vector.body:
10+
; CHECK-NOT: vec.epilog.middle.block:
11+
; CHECK-NOT: vec.epilog.scalar.ph:
12+
;
13+
entry:
14+
%4 = icmp sgt i32 %2, 0
15+
br i1 %4, label %5, label %8
16+
17+
5:
18+
%6 = zext nneg i32 %2 to i64
19+
br label %9
20+
21+
7:
22+
br label %8
23+
24+
8:
25+
ret i32 42
26+
27+
9:
28+
%10 = phi i64 [ 0, %5 ], [ %16, %9 ]
29+
%11 = getelementptr inbounds double, ptr %0, i64 %10
30+
%12 = load double, ptr %11, align 8
31+
%13 = getelementptr inbounds double, ptr %1, i64 %10
32+
%14 = load double, ptr %13, align 8
33+
%15 = fadd fast double %14, %12
34+
store double %15, ptr %11, align 8
35+
%16 = add nuw nsw i64 %10, 1
36+
%17 = icmp eq i64 %16, %6
37+
br i1 %17, label %7, label %9
38+
}
39+
40+
define noundef i32 @V2(ptr noalias nocapture noundef %0, ptr noalias nocapture noundef readonly %1, i32 noundef %2) #1 {
41+
;
42+
; CHECK-LABEL: @V2(
43+
; CHECK: vec.epilog.ph:
44+
; CHECK: vec.epilog.vector.body:
45+
; CHECK: vec.epilog.middle.block:
46+
; CHECK: vec.epilog.scalar.ph:
47+
;
48+
entry:
49+
%4 = icmp sgt i32 %2, 0
50+
br i1 %4, label %5, label %8
51+
52+
5:
53+
%6 = zext nneg i32 %2 to i64
54+
br label %9
55+
56+
7:
57+
br label %8
58+
59+
8:
60+
ret i32 42
61+
62+
9:
63+
%10 = phi i64 [ 0, %5 ], [ %16, %9 ]
64+
%11 = getelementptr inbounds double, ptr %0, i64 %10
65+
%12 = load double, ptr %11, align 8
66+
%13 = getelementptr inbounds double, ptr %1, i64 %10
67+
%14 = load double, ptr %13, align 8
68+
%15 = fadd fast double %14, %12
69+
store double %15, ptr %11, align 8
70+
%16 = add nuw nsw i64 %10, 1
71+
%17 = icmp eq i64 %16, %6
72+
br i1 %17, label %7, label %9
73+
}
74+
75+
; TODO: The V3 will generate a scalable vector body, so doesn't need a
76+
; epilogue loop, but will need to be checked that is really the best thing to
77+
; for the V3.
78+
;
79+
define noundef i32 @V3(ptr noalias nocapture noundef %0, ptr noalias nocapture noundef readonly %1, i32 noundef %2) #2 {
80+
;
81+
; CHECK-LABEL: @V3(
82+
; CHECK-NOT: vec.epilog.ph:
83+
; CHECK-NOT: vec.epilog.vector.body:
84+
; CHECK-NOT: vec.epilog.middle.block:
85+
; CHECK-NOT: vec.epilog.scalar.ph:
86+
;
87+
entry:
88+
%4 = icmp sgt i32 %2, 0
89+
br i1 %4, label %5, label %8
90+
91+
5:
92+
%6 = zext nneg i32 %2 to i64
93+
br label %9
94+
95+
7:
96+
br label %8
97+
98+
8:
99+
ret i32 42
100+
101+
9:
102+
%10 = phi i64 [ 0, %5 ], [ %16, %9 ]
103+
%11 = getelementptr inbounds double, ptr %0, i64 %10
104+
%12 = load double, ptr %11, align 8
105+
%13 = getelementptr inbounds double, ptr %1, i64 %10
106+
%14 = load double, ptr %13, align 8
107+
%15 = fadd fast double %14, %12
108+
store double %15, ptr %11, align 8
109+
%16 = add nuw nsw i64 %10, 1
110+
%17 = icmp eq i64 %16, %6
111+
br i1 %17, label %7, label %9
112+
}
113+
114+
attributes #0 = { vscale_range(1,16) "target-cpu"="neoverse-v1" "target-features"="+sve2" }
115+
116+
attributes #1 = { vscale_range(1,16) "target-cpu"="neoverse-v2" "target-features"="+sve2" }
117+
118+
attributes #2 = { vscale_range(1,16) "target-cpu"="neoverse-v3" "target-features"="+sve2" }

‎llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-vscale-tune.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; RUN: opt -S -passes=loop-vectorize,instsimplify -force-vector-interleave=1 \
22
; RUN: -mcpu=neoverse-v1 -sve-tail-folding=disabled < %s | FileCheck %s --check-prefix=CHECK-EPILOG
33
; RUN: opt -S -passes=loop-vectorize,instsimplify -force-vector-interleave=1 \
4-
; RUN: -mcpu=neoverse-v2 < %s | FileCheck %s --check-prefix=CHECK-NO-EPILOG
4+
; RUN: -mcpu=neoverse-v2 < %s | FileCheck %s --check-prefix=CHECK-EPILOG
55
; RUN: opt -S -passes=loop-vectorize,instsimplify -force-vector-interleave=1 \
66
; RUN: -mcpu=cortex-x2 < %s | FileCheck %s --check-prefix=CHECK-NO-EPILOG
77

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