resolve comments

Author: XinWang10

llvm/lib/Target/X86/X86InstrMisc.td

@@ -1091,15 +1091,15 @@ def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
 // MOVBE Instructions
 //
 multiclass Movbe<bits<8> o, X86TypeInfo t, string suffix = ""> {
-  let SchedRW = [WriteALULd] in
   def rm#suffix : ITy<o, MRMSrcMem, t, (outs t.RegClass:$dst),
                       (ins t.MemOperand:$src1), "movbe", unaryop_ndd_args,
-                      [(set t.RegClass:$dst, (bswap (t.LoadNode addr:$src1)))]>;
-  let SchedRW = [WriteStore] in
+                      [(set t.RegClass:$dst, (bswap (t.LoadNode addr:$src1)))]>,
+                  Sched<[WriteALULd]>;
   def mr#suffix : ITy<!add(o, 1), MRMDestMem, t, (outs),
                       (ins t.MemOperand:$dst, t.RegClass:$src1),
                       "movbe", unaryop_ndd_args,
-                      [(store (bswap t.RegClass:$src1), addr:$dst)]>;
+                      [(store (bswap t.RegClass:$src1), addr:$dst)]>,
+                  Sched<[WriteStore]>;
 }
 
 let Predicates = [HasMOVBE, NoEGPR] in {

llvm/lib/Target/X86/X86InstrRAOINT.td

@@ -27,24 +27,24 @@ def X86rao_and  : SDNode<"X86ISD::AAND", SDTRAOBinaryArith,
 
 multiclass RaoInt<string m, string suffix = ""> {
   let SchedRW = [WriteALURMW, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault] in {
-    def 32mr#suffix : BinOpMR<0xfc, "a"#m, binop_args, Xi32, (outs),
+    def 32mr#suffix : BinOpMR<0xfc, "a" # m, binop_args, Xi32, (outs),
                         [(!cast<SDNode>("X86rao_" # m) addr:$src1, GR32:$src2)]>;
 
-    def 64mr#suffix : BinOpMR<0xfc, "a"#m, binop_args, Xi64, (outs),
+    def 64mr#suffix : BinOpMR<0xfc, "a" # m, binop_args, Xi64, (outs),
                         [(!cast<SDNode>("X86rao_" # m) addr:$src1, GR64:$src2)]>, REX_W;
   }
 }
 
 let Predicates = [HasRAOINT, NoEGPR] in {
-defm AADD : RaoInt<"add">, T8;
-defm AAND : RaoInt<"and">, T8, PD;
-defm AOR  : RaoInt<"or" >, T8, XD;
-defm AXOR : RaoInt<"xor">, T8, XS;
+  defm AADD : RaoInt<"add">, T8;
+  defm AAND : RaoInt<"and">, T8, PD;
+  defm AOR  : RaoInt<"or" >, T8, XD;
+  defm AXOR : RaoInt<"xor">, T8, XS;
 }
 
 let Predicates = [HasRAOINT, HasEGPR, In64BitMode] in {
-defm AADD : RaoInt<"add", "_EVEX">, EVEX, T_MAP4;
-defm AAND : RaoInt<"and", "_EVEX">, EVEX, T_MAP4, PD;
-defm AOR  : RaoInt<"or",  "_EVEX">, EVEX, T_MAP4, XD;
-defm AXOR : RaoInt<"xor", "_EVEX">, EVEX, T_MAP4, XS;
+  defm AADD : RaoInt<"add", "_EVEX">, EVEX, T_MAP4;
+  defm AAND : RaoInt<"and", "_EVEX">, EVEX, T_MAP4, PD;
+  defm AOR  : RaoInt<"or",  "_EVEX">, EVEX, T_MAP4, XD;
+  defm AXOR : RaoInt<"xor", "_EVEX">, EVEX, T_MAP4, XS;
 }

llvm/test/CodeGen/X86/apx/compress-evex.mir

@@ -71,13 +71,3 @@ body:             |
     renamable $rax = XOR64rr_NF_ND killed renamable $rax, killed renamable $r16
     RET64 $rax
 ...
----
-name:            bswapr_to_movberr
-body:             |
-  bb.0.entry:
-    liveins: $rdi
-    ; CHECK: bswapq  %rax                            # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xcf]
-    renamable $rax = MOVBE64rr killed renamable $rdi
-    RET64 killed $rax
-
-...

llvm/test/CodeGen/X86/movbe.ll

@@ -182,7 +182,7 @@ define i64 @test7(i64 %x) nounwind {
 ;
 ; EGPR-LABEL: test7:
 ; EGPR:       # %bb.0:
-; EGPR-NEXT:    bswapq %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xcf]
+; EGPR-NEXT:    movbeq %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x08,0x61,0xf8]
 ; EGPR-NEXT:    retq # encoding: [0xc3]
   %bswap = call i64 @llvm.bswap.i64(i64 %x)
   ret i64 %bswap

llvm/utils/TableGen/X86ManualCompressEVEXTables.def

@@ -328,6 +328,4 @@ ENTRY(VBROADCASTSDZ256rm, VBROADCASTSDYrm)
 ENTRY(VBROADCASTSDZ256rr, VBROADCASTSDYrr)
 ENTRY(VPBROADCASTQZ256rm, VPBROADCASTQYrm)
 ENTRY(VPBROADCASTQZ256rr, VPBROADCASTQYrr)
-ENTRY(MOVBE32rr, BSWAP32r)
-ENTRY(MOVBE64rr, BSWAP64r)
 #undef ENTRY