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[RISCV] Add GHC calling convention
This is a special calling convention to be used by the GHC compiler. Patch by Andreas Schwab (schwab) Differential Revision: https://reviews.llvm.org/D89788
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5 files changed

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‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -325,6 +325,11 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
325325
// to determine the end of the prologue.
326326
DebugLoc DL;
327327

328+
// All calls are tail calls in GHC calling conv, and functions have no
329+
// prologue/epilogue.
330+
if (MF.getFunction().getCallingConv() == CallingConv::GHC)
331+
return;
332+
328333
// Emit prologue for shadow call stack.
329334
emitSCSPrologue(MF, MBB, MBBI, DL);
330335

@@ -500,6 +505,11 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
500505
Register FPReg = getFPReg(STI);
501506
Register SPReg = getSPReg(STI);
502507

508+
// All calls are tail calls in GHC calling conv, and functions have no
509+
// prologue/epilogue.
510+
if (MF.getFunction().getCallingConv() == CallingConv::GHC)
511+
return;
512+
503513
// Get the insert location for the epilogue. If there were no terminators in
504514
// the block, get the last instruction.
505515
MachineBasicBlock::iterator MBBI = MBB.end();

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 62 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -665,6 +665,10 @@ SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
665665

666666
TLSModel::Model Model = getTargetMachine().getTLSModel(N->getGlobal());
667667

668+
if (DAG.getMachineFunction().getFunction().getCallingConv() ==
669+
CallingConv::GHC)
670+
report_fatal_error("In GHC calling convention TLS is not supported");
671+
668672
SDValue Addr;
669673
switch (Model) {
670674
case TLSModel::LocalExec:
@@ -2240,22 +2244,71 @@ static bool CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT,
22402244
return true; // CC didn't match.
22412245
}
22422246

2247+
static bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
2248+
CCValAssign::LocInfo LocInfo,
2249+
ISD::ArgFlagsTy ArgFlags, CCState &State) {
2250+
2251+
if (LocVT == MVT::i32 || LocVT == MVT::i64) {
2252+
// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, SpLim
2253+
// s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11
2254+
static const MCPhysReg GPRList[] = {
2255+
RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22,
2256+
RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27};
2257+
if (unsigned Reg = State.AllocateReg(GPRList)) {
2258+
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2259+
return false;
2260+
}
2261+
}
2262+
2263+
if (LocVT == MVT::f32) {
2264+
// Pass in STG registers: F1, ..., F6
2265+
// fs0 ... fs5
2266+
static const MCPhysReg FPR32List[] = {RISCV::F8_F, RISCV::F9_F,
2267+
RISCV::F18_F, RISCV::F19_F,
2268+
RISCV::F20_F, RISCV::F21_F};
2269+
if (unsigned Reg = State.AllocateReg(FPR32List)) {
2270+
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2271+
return false;
2272+
}
2273+
}
2274+
2275+
if (LocVT == MVT::f64) {
2276+
// Pass in STG registers: D1, ..., D6
2277+
// fs6 ... fs11
2278+
static const MCPhysReg FPR64List[] = {RISCV::F22_D, RISCV::F23_D,
2279+
RISCV::F24_D, RISCV::F25_D,
2280+
RISCV::F26_D, RISCV::F27_D};
2281+
if (unsigned Reg = State.AllocateReg(FPR64List)) {
2282+
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2283+
return false;
2284+
}
2285+
}
2286+
2287+
report_fatal_error("No registers left in GHC calling convention");
2288+
return true;
2289+
}
2290+
22432291
// Transform physical registers into virtual registers.
22442292
SDValue RISCVTargetLowering::LowerFormalArguments(
22452293
SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
22462294
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
22472295
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
22482296

2297+
MachineFunction &MF = DAG.getMachineFunction();
2298+
22492299
switch (CallConv) {
22502300
default:
22512301
report_fatal_error("Unsupported calling convention");
22522302
case CallingConv::C:
22532303
case CallingConv::Fast:
22542304
break;
2305+
case CallingConv::GHC:
2306+
if (!MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtF] ||
2307+
!MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtD])
2308+
report_fatal_error(
2309+
"GHC calling convention requires the F and D instruction set extensions");
22552310
}
22562311

2257-
MachineFunction &MF = DAG.getMachineFunction();
2258-
22592312
const Function &Func = MF.getFunction();
22602313
if (Func.hasFnAttribute("interrupt")) {
22612314
if (!Func.arg_empty())
@@ -2282,6 +2335,8 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
22822335

22832336
if (CallConv == CallingConv::Fast)
22842337
CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_FastCC);
2338+
else if (CallConv == CallingConv::GHC)
2339+
CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_GHC);
22852340
else
22862341
analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false);
22872342

@@ -2482,6 +2537,8 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
24822537

24832538
if (CallConv == CallingConv::Fast)
24842539
ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_FastCC);
2540+
else if (CallConv == CallingConv::GHC)
2541+
ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_GHC);
24852542
else
24862543
analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI);
24872544

@@ -2769,6 +2826,9 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
27692826
analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true,
27702827
nullptr);
27712828

2829+
if (CallConv == CallingConv::GHC && !RVLocs.empty())
2830+
report_fatal_error("GHC functions return void only");
2831+
27722832
SDValue Glue;
27732833
SmallVector<SDValue, 4> RetOps(1, Chain);
27742834

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,8 @@ RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
4545
const MCPhysReg *
4646
RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
4747
auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
48+
if (MF->getFunction().getCallingConv() == CallingConv::GHC)
49+
return CSR_NoRegs_SaveList;
4850
if (MF->getFunction().hasFnAttribute("interrupt")) {
4951
if (Subtarget.hasStdExtD())
5052
return CSR_XLEN_F64_Interrupt_SaveList;
@@ -191,9 +193,11 @@ Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
191193

192194
const uint32_t *
193195
RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
194-
CallingConv::ID /*CC*/) const {
196+
CallingConv::ID CC) const {
195197
auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
196198

199+
if (CC == CallingConv::GHC)
200+
return CSR_NoRegs_RegMask;
197201
switch (Subtarget.getTargetABI()) {
198202
default:
199203
llvm_unreachable("Unrecognized ABI");

‎llvm/test/CodeGen/RISCV/ghccc-rv32.ll

Lines changed: 114 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,114 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -mattr=+f,+d < %s | FileCheck %s
3+
4+
; Check the GHC call convention works (rv32)
5+
6+
@base = external global i32 ; assigned to register: s1
7+
@sp = external global i32 ; assigned to register: s2
8+
@hp = external global i32 ; assigned to register: s3
9+
@r1 = external global i32 ; assigned to register: s4
10+
@r2 = external global i32 ; assigned to register: s5
11+
@r3 = external global i32 ; assigned to register: s6
12+
@r4 = external global i32 ; assigned to register: s7
13+
@r5 = external global i32 ; assigned to register: s8
14+
@r6 = external global i32 ; assigned to register: s9
15+
@r7 = external global i32 ; assigned to register: s10
16+
@splim = external global i32 ; assigned to register: s11
17+
18+
@f1 = external global float ; assigned to register: fs0
19+
@f2 = external global float ; assigned to register: fs1
20+
@f3 = external global float ; assigned to register: fs2
21+
@f4 = external global float ; assigned to register: fs3
22+
@f5 = external global float ; assigned to register: fs4
23+
@f6 = external global float ; assigned to register: fs5
24+
25+
@d1 = external global double ; assigned to register: fs6
26+
@d2 = external global double ; assigned to register: fs7
27+
@d3 = external global double ; assigned to register: fs8
28+
@d4 = external global double ; assigned to register: fs9
29+
@d5 = external global double ; assigned to register: fs10
30+
@d6 = external global double ; assigned to register: fs11
31+
32+
define ghccc void @foo() nounwind {
33+
; CHECK-LABEL: foo:
34+
; CHECK: # %bb.0: # %entry
35+
; CHECK-NEXT: lui a0, %hi(d6)
36+
; CHECK-NEXT: fld fs11, %lo(d6)(a0)
37+
; CHECK-NEXT: lui a0, %hi(d5)
38+
; CHECK-NEXT: fld fs10, %lo(d5)(a0)
39+
; CHECK-NEXT: lui a0, %hi(d4)
40+
; CHECK-NEXT: fld fs9, %lo(d4)(a0)
41+
; CHECK-NEXT: lui a0, %hi(d3)
42+
; CHECK-NEXT: fld fs8, %lo(d3)(a0)
43+
; CHECK-NEXT: lui a0, %hi(d2)
44+
; CHECK-NEXT: fld fs7, %lo(d2)(a0)
45+
; CHECK-NEXT: lui a0, %hi(d1)
46+
; CHECK-NEXT: fld fs6, %lo(d1)(a0)
47+
; CHECK-NEXT: lui a0, %hi(f6)
48+
; CHECK-NEXT: flw fs5, %lo(f6)(a0)
49+
; CHECK-NEXT: lui a0, %hi(f5)
50+
; CHECK-NEXT: flw fs4, %lo(f5)(a0)
51+
; CHECK-NEXT: lui a0, %hi(f4)
52+
; CHECK-NEXT: flw fs3, %lo(f4)(a0)
53+
; CHECK-NEXT: lui a0, %hi(f3)
54+
; CHECK-NEXT: flw fs2, %lo(f3)(a0)
55+
; CHECK-NEXT: lui a0, %hi(f2)
56+
; CHECK-NEXT: flw fs1, %lo(f2)(a0)
57+
; CHECK-NEXT: lui a0, %hi(f1)
58+
; CHECK-NEXT: flw fs0, %lo(f1)(a0)
59+
; CHECK-NEXT: lui a0, %hi(splim)
60+
; CHECK-NEXT: lw s11, %lo(splim)(a0)
61+
; CHECK-NEXT: lui a0, %hi(r7)
62+
; CHECK-NEXT: lw s10, %lo(r7)(a0)
63+
; CHECK-NEXT: lui a0, %hi(r6)
64+
; CHECK-NEXT: lw s9, %lo(r6)(a0)
65+
; CHECK-NEXT: lui a0, %hi(r5)
66+
; CHECK-NEXT: lw s8, %lo(r5)(a0)
67+
; CHECK-NEXT: lui a0, %hi(r4)
68+
; CHECK-NEXT: lw s7, %lo(r4)(a0)
69+
; CHECK-NEXT: lui a0, %hi(r3)
70+
; CHECK-NEXT: lw s6, %lo(r3)(a0)
71+
; CHECK-NEXT: lui a0, %hi(r2)
72+
; CHECK-NEXT: lw s5, %lo(r2)(a0)
73+
; CHECK-NEXT: lui a0, %hi(r1)
74+
; CHECK-NEXT: lw s4, %lo(r1)(a0)
75+
; CHECK-NEXT: lui a0, %hi(hp)
76+
; CHECK-NEXT: lw s3, %lo(hp)(a0)
77+
; CHECK-NEXT: lui a0, %hi(sp)
78+
; CHECK-NEXT: lw s2, %lo(sp)(a0)
79+
; CHECK-NEXT: lui a0, %hi(base)
80+
; CHECK-NEXT: lw s1, %lo(base)(a0)
81+
; CHECK-NEXT: tail bar
82+
entry:
83+
%0 = load double, double* @d6
84+
%1 = load double, double* @d5
85+
%2 = load double, double* @d4
86+
%3 = load double, double* @d3
87+
%4 = load double, double* @d2
88+
%5 = load double, double* @d1
89+
%6 = load float, float* @f6
90+
%7 = load float, float* @f5
91+
%8 = load float, float* @f4
92+
%9 = load float, float* @f3
93+
%10 = load float, float* @f2
94+
%11 = load float, float* @f1
95+
%12 = load i32, i32* @splim
96+
%13 = load i32, i32* @r7
97+
%14 = load i32, i32* @r6
98+
%15 = load i32, i32* @r5
99+
%16 = load i32, i32* @r4
100+
%17 = load i32, i32* @r3
101+
%18 = load i32, i32* @r2
102+
%19 = load i32, i32* @r1
103+
%20 = load i32, i32* @hp
104+
%21 = load i32, i32* @sp
105+
%22 = load i32, i32* @base
106+
tail call ghccc void @bar(i32 %22, i32 %21, i32 %20, i32 %19, i32 %18, i32 %17, i32 %16, i32 %15, i32 %14, i32 %13, i32 %12,
107+
float %11, float %10, float %9, float %8, float %7, float %6,
108+
double %5, double %4, double %3, double %2, double %1, double %0) nounwind
109+
ret void
110+
}
111+
112+
declare ghccc void @bar(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
113+
float, float, float, float, float, float,
114+
double, double, double, double, double, double)

‎llvm/test/CodeGen/RISCV/ghccc-rv64.ll

Lines changed: 114 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,114 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv64 -mattr=+f,+d < %s | FileCheck %s
3+
4+
; Check the GHC call convention works (rv64)
5+
6+
@base = external global i64 ; assigned to register: s1
7+
@sp = external global i64 ; assigned to register: s2
8+
@hp = external global i64 ; assigned to register: s3
9+
@r1 = external global i64 ; assigned to register: s4
10+
@r2 = external global i64 ; assigned to register: s5
11+
@r3 = external global i64 ; assigned to register: s6
12+
@r4 = external global i64 ; assigned to register: s7
13+
@r5 = external global i64 ; assigned to register: s8
14+
@r6 = external global i64 ; assigned to register: s9
15+
@r7 = external global i64 ; assigned to register: s10
16+
@splim = external global i64 ; assigned to register: s11
17+
18+
@f1 = external global float ; assigned to register: fs0
19+
@f2 = external global float ; assigned to register: fs1
20+
@f3 = external global float ; assigned to register: fs2
21+
@f4 = external global float ; assigned to register: fs3
22+
@f5 = external global float ; assigned to register: fs4
23+
@f6 = external global float ; assigned to register: fs5
24+
25+
@d1 = external global double ; assigned to register: fs6
26+
@d2 = external global double ; assigned to register: fs7
27+
@d3 = external global double ; assigned to register: fs8
28+
@d4 = external global double ; assigned to register: fs9
29+
@d5 = external global double ; assigned to register: fs10
30+
@d6 = external global double ; assigned to register: fs11
31+
32+
define ghccc void @foo() nounwind {
33+
; CHECK-LABEL: foo:
34+
; CHECK: # %bb.0: # %entry
35+
; CHECK-NEXT: lui a0, %hi(d6)
36+
; CHECK-NEXT: fld fs11, %lo(d6)(a0)
37+
; CHECK-NEXT: lui a0, %hi(d5)
38+
; CHECK-NEXT: fld fs10, %lo(d5)(a0)
39+
; CHECK-NEXT: lui a0, %hi(d4)
40+
; CHECK-NEXT: fld fs9, %lo(d4)(a0)
41+
; CHECK-NEXT: lui a0, %hi(d3)
42+
; CHECK-NEXT: fld fs8, %lo(d3)(a0)
43+
; CHECK-NEXT: lui a0, %hi(d2)
44+
; CHECK-NEXT: fld fs7, %lo(d2)(a0)
45+
; CHECK-NEXT: lui a0, %hi(d1)
46+
; CHECK-NEXT: fld fs6, %lo(d1)(a0)
47+
; CHECK-NEXT: lui a0, %hi(f6)
48+
; CHECK-NEXT: flw fs5, %lo(f6)(a0)
49+
; CHECK-NEXT: lui a0, %hi(f5)
50+
; CHECK-NEXT: flw fs4, %lo(f5)(a0)
51+
; CHECK-NEXT: lui a0, %hi(f4)
52+
; CHECK-NEXT: flw fs3, %lo(f4)(a0)
53+
; CHECK-NEXT: lui a0, %hi(f3)
54+
; CHECK-NEXT: flw fs2, %lo(f3)(a0)
55+
; CHECK-NEXT: lui a0, %hi(f2)
56+
; CHECK-NEXT: flw fs1, %lo(f2)(a0)
57+
; CHECK-NEXT: lui a0, %hi(f1)
58+
; CHECK-NEXT: flw fs0, %lo(f1)(a0)
59+
; CHECK-NEXT: lui a0, %hi(splim)
60+
; CHECK-NEXT: ld s11, %lo(splim)(a0)
61+
; CHECK-NEXT: lui a0, %hi(r7)
62+
; CHECK-NEXT: ld s10, %lo(r7)(a0)
63+
; CHECK-NEXT: lui a0, %hi(r6)
64+
; CHECK-NEXT: ld s9, %lo(r6)(a0)
65+
; CHECK-NEXT: lui a0, %hi(r5)
66+
; CHECK-NEXT: ld s8, %lo(r5)(a0)
67+
; CHECK-NEXT: lui a0, %hi(r4)
68+
; CHECK-NEXT: ld s7, %lo(r4)(a0)
69+
; CHECK-NEXT: lui a0, %hi(r3)
70+
; CHECK-NEXT: ld s6, %lo(r3)(a0)
71+
; CHECK-NEXT: lui a0, %hi(r2)
72+
; CHECK-NEXT: ld s5, %lo(r2)(a0)
73+
; CHECK-NEXT: lui a0, %hi(r1)
74+
; CHECK-NEXT: ld s4, %lo(r1)(a0)
75+
; CHECK-NEXT: lui a0, %hi(hp)
76+
; CHECK-NEXT: ld s3, %lo(hp)(a0)
77+
; CHECK-NEXT: lui a0, %hi(sp)
78+
; CHECK-NEXT: ld s2, %lo(sp)(a0)
79+
; CHECK-NEXT: lui a0, %hi(base)
80+
; CHECK-NEXT: ld s1, %lo(base)(a0)
81+
; CHECK-NEXT: tail bar
82+
entry:
83+
%0 = load double, double* @d6
84+
%1 = load double, double* @d5
85+
%2 = load double, double* @d4
86+
%3 = load double, double* @d3
87+
%4 = load double, double* @d2
88+
%5 = load double, double* @d1
89+
%6 = load float, float* @f6
90+
%7 = load float, float* @f5
91+
%8 = load float, float* @f4
92+
%9 = load float, float* @f3
93+
%10 = load float, float* @f2
94+
%11 = load float, float* @f1
95+
%12 = load i64, i64* @splim
96+
%13 = load i64, i64* @r7
97+
%14 = load i64, i64* @r6
98+
%15 = load i64, i64* @r5
99+
%16 = load i64, i64* @r4
100+
%17 = load i64, i64* @r3
101+
%18 = load i64, i64* @r2
102+
%19 = load i64, i64* @r1
103+
%20 = load i64, i64* @hp
104+
%21 = load i64, i64* @sp
105+
%22 = load i64, i64* @base
106+
tail call ghccc void @bar(i64 %22, i64 %21, i64 %20, i64 %19, i64 %18, i64 %17, i64 %16, i64 %15, i64 %14, i64 %13, i64 %12,
107+
float %11, float %10, float %9, float %8, float %7, float %6,
108+
double %5, double %4, double %3, double %2, double %1, double %0) nounwind
109+
ret void
110+
}
111+
112+
declare ghccc void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64,
113+
float, float, float, float, float, float,
114+
double, double, double, double, double, double)

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