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[NFC][LLVM] Make s_getpc_b64 rematerializable
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‎llvm/test/CodeGen/AMDGPU/remat-sop.mir

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Original file line numberDiff line numberDiff line change
@@ -573,3 +573,92 @@ body: |
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S_NOP 0, implicit %2
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S_ENDPGM 0
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...
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---
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name: test_remat_s_getpc_b64
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: test_remat_s_getpc_b64
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; GCN: renamable $sgpr0_sgpr1 = S_GETPC_B64
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; GCN-NEXT: SI_SPILL_S64_SAVE killed renamable $sgpr0_sgpr1, %stack.1, implicit $exec, implicit $sp_reg :: (store (s64) into %stack.1, align 4, addrspace 5)
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; GCN-NEXT: renamable $sgpr2_sgpr3 = S_GETPC_B64
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; GCN-NEXT: renamable $sgpr0_sgpr1 = S_GETPC_B64
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; GCN-NEXT: SI_SPILL_S64_SAVE killed renamable $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sp_reg :: (store (s64) into %stack.0, align 4, addrspace 5)
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; GCN-NEXT: renamable $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sp_reg :: (load (s64) from %stack.1, align 4, addrspace 5)
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; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
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; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr2_sgpr3
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; GCN-NEXT: renamable $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load (s64) from %stack.0, align 4, addrspace 5)
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; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
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; GCN-NEXT: S_ENDPGM 0
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%0:sgpr_64 = S_GETPC_B64
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%1:sgpr_64 = S_GETPC_B64
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%2:sgpr_64 = S_GETPC_B64
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S_NOP 0, implicit %0
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S_NOP 0, implicit %1
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S_NOP 0, implicit %2
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S_ENDPGM 0
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...
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---
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name: test_remat_s_getpc_b64_2
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: test_remat_s_getpc_b64_2
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; GCN: renamable $sgpr0_sgpr1 = S_GETPC_B64
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; GCN-NEXT: renamable $sgpr2_sgpr3 = S_GETPC_B64
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; GCN-NEXT: SI_SPILL_S64_SAVE killed renamable $sgpr2_sgpr3, %stack.7, implicit $exec, implicit $sp_reg :: (store (s64) into %stack.7, align 4, addrspace 5)
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; GCN-NEXT: renamable $sgpr2_sgpr3 = S_GETPC_B64
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; GCN-NEXT: SI_SPILL_S64_SAVE killed renamable $sgpr2_sgpr3, %stack.6, implicit $exec, implicit $sp_reg :: (store (s64) into %stack.6, align 4, addrspace 5)
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; GCN-NEXT: SI_SPILL_S32_SAVE killed renamable $sgpr0, %stack.3, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.3, addrspace 5)
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; GCN-NEXT: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.0, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.0, addrspace 5)
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; GCN-NEXT: renamable $sgpr2_sgpr3 = SI_SPILL_S64_RESTORE %stack.7, implicit $exec, implicit $sp_reg :: (load (s64) from %stack.7, align 4, addrspace 5)
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; GCN-NEXT: renamable $sgpr1 = COPY renamable $sgpr2
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; GCN-NEXT: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.1, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.1, addrspace 5)
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; GCN-NEXT: renamable $sgpr1 = COPY killed renamable $sgpr3
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; GCN-NEXT: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.2, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.2, addrspace 5)
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; GCN-NEXT: renamable $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.6, implicit $exec, implicit $sp_reg :: (load (s64) from %stack.6, align 4, addrspace 5)
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; GCN-NEXT: SI_SPILL_S32_SAVE killed renamable $sgpr0, %stack.5, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.5, addrspace 5)
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; GCN-NEXT: renamable $sgpr0 = COPY killed renamable $sgpr1
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; GCN-NEXT: SI_SPILL_S32_SAVE killed renamable $sgpr0, %stack.4, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.4, addrspace 5)
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; GCN-NEXT: renamable $sgpr0 = SI_SPILL_S32_RESTORE %stack.1, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.1, addrspace 5)
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; GCN-NEXT: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.3, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.3, addrspace 5)
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; GCN-NEXT: dead renamable $sgpr0 = S_ADD_U32 killed renamable $sgpr1, killed renamable $sgpr0, implicit-def $scc
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; GCN-NEXT: renamable $sgpr0 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.0, addrspace 5)
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; GCN-NEXT: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.2, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.2, addrspace 5)
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; GCN-NEXT: dead renamable $sgpr0 = S_ADDC_U32 killed renamable $sgpr0, killed renamable $sgpr1, implicit-def $scc, implicit $scc
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; GCN-NEXT: renamable $sgpr0 = SI_SPILL_S32_RESTORE %stack.3, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.3, addrspace 5)
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; GCN-NEXT: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.5, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.5, addrspace 5)
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; GCN-NEXT: dead renamable $sgpr0 = S_ADD_U32 killed renamable $sgpr0, killed renamable $sgpr1, implicit-def $scc
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; GCN-NEXT: renamable $sgpr0 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.0, addrspace 5)
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; GCN-NEXT: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.4, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.4, addrspace 5)
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; GCN-NEXT: dead renamable $sgpr0 = S_ADDC_U32 killed renamable $sgpr0, killed renamable $sgpr1, implicit-def $scc, implicit $scc
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; GCN-NEXT: renamable $sgpr0 = SI_SPILL_S32_RESTORE %stack.1, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.1, addrspace 5)
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; GCN-NEXT: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.5, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.5, addrspace 5)
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; GCN-NEXT: dead renamable $sgpr0 = S_ADD_U32 killed renamable $sgpr0, killed renamable $sgpr1, implicit-def $scc
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; GCN-NEXT: renamable $sgpr0 = SI_SPILL_S32_RESTORE %stack.2, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.2, addrspace 5)
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; GCN-NEXT: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.4, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.4, addrspace 5)
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; GCN-NEXT: dead renamable $sgpr0 = S_ADDC_U32 killed renamable $sgpr0, killed renamable $sgpr1, implicit-def $scc, implicit $scc
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; GCN-NEXT: S_ENDPGM 0
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%0:sreg_64 = S_GETPC_B64
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%1:sreg_64 = S_GETPC_B64
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%2:sreg_64 = S_GETPC_B64
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%4:sreg_32 = COPY %0.sub0:sreg_64
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%5:sreg_32 = COPY %0.sub1:sreg_64
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%6:sreg_32 = COPY %1.sub0:sreg_64
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%7:sreg_32 = COPY %1.sub1:sreg_64
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%8:sreg_32 = COPY %2.sub0:sreg_64
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%9:sreg_32 = COPY %2.sub1:sreg_64
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%10:sreg_32 = S_ADD_U32 %4:sreg_32, %6:sreg_32, implicit-def $scc
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%11:sreg_32 = S_ADDC_U32 %5:sreg_32, %7:sreg_32, implicit-def $scc, implicit $scc
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%12:sreg_32 = S_ADD_U32 %4:sreg_32, %8:sreg_32, implicit-def $scc
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%13:sreg_32 = S_ADDC_U32 %5:sreg_32, %9:sreg_32, implicit-def $scc, implicit $scc
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%14:sreg_32 = S_ADD_U32 %6:sreg_32, %8:sreg_32, implicit-def $scc
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%15:sreg_32 = S_ADDC_U32 %7:sreg_32, %9:sreg_32, implicit-def $scc, implicit $scc
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S_ENDPGM 0
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...
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‎llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll

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@@ -0,0 +1,45 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stress-regalloc=2 -verify-machineinstrs < %s | FileCheck %s
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define void @test_remat_s_getpc_b64() {
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; CHECK-LABEL: test_remat_s_getpc_b64:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
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; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
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; CHECK-NEXT: s_mov_b64 exec, s[4:5]
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; CHECK-NEXT: ; implicit-def: $vgpr1 : SGPR spill to VGPR lane
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; CHECK-NEXT: s_getpc_b64 s[4:5]
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; CHECK-NEXT: v_writelane_b32 v0, s30, 0
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; CHECK-NEXT: v_writelane_b32 v1, s4, 0
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; CHECK-NEXT: v_writelane_b32 v0, s31, 1
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; CHECK-NEXT: v_writelane_b32 v1, s5, 1
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_readlane_b32 s4, v1, 0
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; CHECK-NEXT: v_readlane_b32 s5, v1, 1
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; CHECK-NEXT: v_mov_b32_e32 v2, s4
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; CHECK-NEXT: v_mov_b32_e32 v3, s5
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; CHECK-NEXT: global_store_dwordx2 v[1:2], v[2:3], off
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; CHECK-NEXT: v_readlane_b32 s31, v0, 1
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; CHECK-NEXT: v_readlane_b32 s30, v0, 0
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; CHECK-NEXT: ; kill: killed $vgpr1
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; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
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; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
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; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
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; CHECK-NEXT: s_mov_b64 exec, s[4:5]
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%0 = tail call i64 @llvm.amdgcn.s.getpc()
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tail call void asm sideeffect "", "s"(i64 %0)
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tail call void asm sideeffect "", "~{s0},~{s1},~{s2},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"()
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store i64 %0, ptr addrspace(1) undef
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ret void
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}
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declare i64 @llvm.amdgcn.s.getpc()

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