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VE
1 parent 5a880e4 commit a91bae6

10 files changed

+110
-93
lines changed

llvm/lib/Target/VE/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ tablegen(LLVM VEGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM VEGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM VEGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM VEGenDAGISel.inc -gen-dag-isel)
12+
tablegen(LLVM VEGenSDNodeInfo.inc -gen-sd-node-info)
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tablegen(LLVM VEGenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM VEGenCallingConv.inc -gen-callingconv)
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add_public_tablegen_target(VECommonTableGen)
@@ -24,6 +25,7 @@ add_llvm_target(VECodeGen
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VEMachineFunctionInfo.cpp
2526
VEMCInstLower.cpp
2627
VERegisterInfo.cpp
28+
VESelectionDAGInfo.cpp
2729
VESubtarget.cpp
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VETargetMachine.cpp
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VVPISelLowering.cpp

llvm/lib/Target/VE/VECustomDAG.cpp

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@@ -12,6 +12,7 @@
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//===----------------------------------------------------------------------===//
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#include "VECustomDAG.h"
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#include "VESelectionDAGInfo.h"
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#ifndef DEBUG_TYPE
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#define DEBUG_TYPE "vecustomdag"

llvm/lib/Target/VE/VEISelDAGToDAG.cpp

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@@ -11,6 +11,7 @@
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//===----------------------------------------------------------------------===//
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#include "VE.h"
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#include "VESelectionDAGInfo.h"
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#include "VETargetMachine.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Support/ErrorHandling.h"

llvm/lib/Target/VE/VEISelLowering.cpp

Lines changed: 1 addition & 41 deletions
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@@ -17,6 +17,7 @@
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#include "VEInstrBuilder.h"
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#include "VEMachineFunctionInfo.h"
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#include "VERegisterInfo.h"
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#include "VESelectionDAGInfo.h"
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#include "VETargetMachine.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/CodeGen/CallingConvLower.h"
@@ -923,47 +924,6 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
923924
computeRegisterProperties(Subtarget->getRegisterInfo());
924925
}
925926

926-
const char *VETargetLowering::getTargetNodeName(unsigned Opcode) const {
927-
#define TARGET_NODE_CASE(NAME) \
928-
case VEISD::NAME: \
929-
return "VEISD::" #NAME;
930-
switch ((VEISD::NodeType)Opcode) {
931-
case VEISD::FIRST_NUMBER:
932-
break;
933-
TARGET_NODE_CASE(CMPI)
934-
TARGET_NODE_CASE(CMPU)
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TARGET_NODE_CASE(CMPF)
936-
TARGET_NODE_CASE(CMPQ)
937-
TARGET_NODE_CASE(CMOV)
938-
TARGET_NODE_CASE(CALL)
939-
TARGET_NODE_CASE(EH_SJLJ_LONGJMP)
940-
TARGET_NODE_CASE(EH_SJLJ_SETJMP)
941-
TARGET_NODE_CASE(EH_SJLJ_SETUP_DISPATCH)
942-
TARGET_NODE_CASE(GETFUNPLT)
943-
TARGET_NODE_CASE(GETSTACKTOP)
944-
TARGET_NODE_CASE(GETTLSADDR)
945-
TARGET_NODE_CASE(GLOBAL_BASE_REG)
946-
TARGET_NODE_CASE(Hi)
947-
TARGET_NODE_CASE(Lo)
948-
TARGET_NODE_CASE(RET_GLUE)
949-
TARGET_NODE_CASE(TS1AM)
950-
TARGET_NODE_CASE(VEC_UNPACK_LO)
951-
TARGET_NODE_CASE(VEC_UNPACK_HI)
952-
TARGET_NODE_CASE(VEC_PACK)
953-
TARGET_NODE_CASE(VEC_BROADCAST)
954-
TARGET_NODE_CASE(REPL_I32)
955-
TARGET_NODE_CASE(REPL_F32)
956-
957-
TARGET_NODE_CASE(LEGALAVL)
958-
959-
// Register the VVP_* SDNodes.
960-
#define ADD_VVP_OP(VVP_NAME, ...) TARGET_NODE_CASE(VVP_NAME)
961-
#include "VVPNodes.def"
962-
}
963-
#undef TARGET_NODE_CASE
964-
return nullptr;
965-
}
966-
967927
EVT VETargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
968928
EVT VT) const {
969929
return MVT::i32;

llvm/lib/Target/VE/VEISelLowering.h

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@@ -20,51 +20,6 @@
2020
namespace llvm {
2121
class VESubtarget;
2222

23-
namespace VEISD {
24-
enum NodeType : unsigned {
25-
FIRST_NUMBER = ISD::BUILTIN_OP_END,
26-
27-
CMPI, // Compare between two signed integer values.
28-
CMPU, // Compare between two unsigned integer values.
29-
CMPF, // Compare between two floating-point values.
30-
CMPQ, // Compare between two quad floating-point values.
31-
CMOV, // Select between two values using the result of comparison.
32-
33-
CALL, // A call instruction.
34-
EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
35-
EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
36-
EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
37-
GETFUNPLT, // Load function address through %plt insturction.
38-
GETTLSADDR, // Load address for TLS access.
39-
GETSTACKTOP, // Retrieve address of stack top (first address of
40-
// locals and temporaries).
41-
GLOBAL_BASE_REG, // Global base reg for PIC.
42-
Hi, // Hi/Lo operations, typically on a global address.
43-
Lo, // Hi/Lo operations, typically on a global address.
44-
RET_GLUE, // Return with a flag operand.
45-
TS1AM, // A TS1AM instruction used for 1/2 bytes swap.
46-
VEC_UNPACK_LO, // unpack the lo v256 slice of a packed v512 vector.
47-
VEC_UNPACK_HI, // unpack the hi v256 slice of a packed v512 vector.
48-
// 0: v512 vector, 1: AVL
49-
VEC_PACK, // pack a lo and a hi vector into one v512 vector
50-
// 0: v256 lo vector, 1: v256 hi vector, 2: AVL
51-
52-
VEC_BROADCAST, // A vector broadcast instruction.
53-
// 0: scalar value, 1: VL
54-
REPL_I32,
55-
REPL_F32, // Replicate subregister to other half.
56-
57-
// Annotation as a wrapper. LEGALAVL(VL) means that VL refers to 64bit of
58-
// data, whereas the raw EVL coming in from VP nodes always refers to number
59-
// of elements, regardless of their size.
60-
LEGALAVL,
61-
62-
// VVP_* nodes.
63-
#define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME,
64-
#include "VVPNodes.def"
65-
};
66-
}
67-
6823
/// Convert a DAG integer condition code to a VE ICC condition.
6924
inline static VECC::CondCode intCondCode2Icc(ISD::CondCode CC) {
7025
switch (CC) {
@@ -167,7 +122,6 @@ class VETargetLowering : public TargetLowering {
167122
public:
168123
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
169124

170-
const char *getTargetNodeName(unsigned Opcode) const override;
171125
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
172126
return MVT::i32;
173127
}
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@@ -0,0 +1,44 @@
1+
//===- VESelectionDAGInfo.cpp ---------------------------------------------===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
9+
#include "VESelectionDAGInfo.h"
10+
11+
#define GET_SDNODE_DESC
12+
#include "VEGenSDNodeInfo.inc"
13+
14+
using namespace llvm;
15+
16+
VESelectionDAGInfo::VESelectionDAGInfo()
17+
: SelectionDAGGenTargetInfo(VEGenSDNodeInfo) {}
18+
19+
VESelectionDAGInfo::~VESelectionDAGInfo() = default;
20+
21+
const char *VESelectionDAGInfo::getTargetNodeName(unsigned Opcode) const {
22+
#define TARGET_NODE_CASE(NAME) \
23+
case VEISD::NAME: \
24+
return "VEISD::" #NAME;
25+
26+
switch (static_cast<VEISD::NodeType>(Opcode)) {
27+
TARGET_NODE_CASE(GLOBAL_BASE_REG)
28+
TARGET_NODE_CASE(LEGALAVL)
29+
}
30+
#undef TARGET_NODE_CASE
31+
32+
return SelectionDAGGenTargetInfo::getTargetNodeName(Opcode);
33+
}
34+
35+
void VESelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
36+
const SDNode *N) const {
37+
switch (N->getOpcode()) {
38+
case VEISD::GETSTACKTOP:
39+
// result #0 has invalid type; expected ch, got i64
40+
return;
41+
}
42+
43+
SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
44+
}
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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
//===- VESelectionDAGInfo.h -------------------------------------*- C++ -*-===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
9+
#ifndef LLVM_LIB_TARGET_VE_VESELECTIONDAGINFO_H
10+
#define LLVM_LIB_TARGET_VE_VESELECTIONDAGINFO_H
11+
12+
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
13+
14+
#define GET_SDNODE_ENUM
15+
#include "VEGenSDNodeInfo.inc"
16+
17+
namespace llvm {
18+
namespace VEISD {
19+
20+
enum NodeType : unsigned {
21+
GLOBAL_BASE_REG = GENERATED_OPCODE_END, // Global base reg for PIC.
22+
23+
// Annotation as a wrapper. LEGALAVL(VL) means that VL refers to 64bit of
24+
// data, whereas the raw EVL coming in from VP nodes always refers to number
25+
// of elements, regardless of their size.
26+
LEGALAVL,
27+
};
28+
29+
} // namespace VEISD
30+
31+
class VESelectionDAGInfo : public SelectionDAGGenTargetInfo {
32+
public:
33+
VESelectionDAGInfo();
34+
35+
~VESelectionDAGInfo() override;
36+
37+
const char *getTargetNodeName(unsigned Opcode) const override;
38+
39+
void verifyTargetNode(const SelectionDAG &DAG,
40+
const SDNode *N) const override;
41+
};
42+
43+
} // namespace llvm
44+
45+
#endif // LLVM_LIB_TARGET_VE_VESELECTIONDAGINFO_H

llvm/lib/Target/VE/VESubtarget.cpp

Lines changed: 10 additions & 1 deletion
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@@ -11,6 +11,7 @@
1111
//===----------------------------------------------------------------------===//
1212

1313
#include "VESubtarget.h"
14+
#include "VESelectionDAGInfo.h"
1415
#include "llvm/MC/TargetRegistry.h"
1516

1617
using namespace llvm;
@@ -43,7 +44,15 @@ VESubtarget::VESubtarget(const Triple &TT, const std::string &CPU,
4344
const std::string &FS, const TargetMachine &TM)
4445
: VEGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), TargetTriple(TT),
4546
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
46-
FrameLowering(*this) {}
47+
FrameLowering(*this) {
48+
TSInfo = std::make_unique<VESelectionDAGInfo>();
49+
}
50+
51+
VESubtarget::~VESubtarget() = default;
52+
53+
const SelectionDAGTargetInfo *VESubtarget::getSelectionDAGInfo() const {
54+
return TSInfo.get();
55+
}
4756

4857
uint64_t VESubtarget::getAdjustedFrameSize(uint64_t FrameSize) const {
4958
// Calculate adjusted frame size by adding the size of RSA frame,

llvm/lib/Target/VE/VESubtarget.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,6 @@
1616
#include "VEFrameLowering.h"
1717
#include "VEISelLowering.h"
1818
#include "VEInstrInfo.h"
19-
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
2019
#include "llvm/CodeGen/TargetFrameLowering.h"
2120
#include "llvm/CodeGen/TargetSubtargetInfo.h"
2221
#include "llvm/IR/DataLayout.h"
@@ -41,13 +40,15 @@ class VESubtarget : public VEGenSubtargetInfo {
4140

4241
VEInstrInfo InstrInfo;
4342
VETargetLowering TLInfo;
44-
SelectionDAGTargetInfo TSInfo;
43+
std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
4544
VEFrameLowering FrameLowering;
4645

4746
public:
4847
VESubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
4948
const TargetMachine &TM);
5049

50+
~VESubtarget() override;
51+
5152
const VEInstrInfo *getInstrInfo() const override { return &InstrInfo; }
5253
const VEFrameLowering *getFrameLowering() const override {
5354
return &FrameLowering;
@@ -56,9 +57,8 @@ class VESubtarget : public VEGenSubtargetInfo {
5657
return &InstrInfo.getRegisterInfo();
5758
}
5859
const VETargetLowering *getTargetLowering() const override { return &TLInfo; }
59-
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
60-
return &TSInfo;
61-
}
60+
61+
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
6262

6363
bool enableMachineScheduler() const override;
6464

llvm/lib/Target/VE/VVPISelLowering.cpp

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@@ -13,6 +13,7 @@
1313

1414
#include "VECustomDAG.h"
1515
#include "VEISelLowering.h"
16+
#include "VESelectionDAGInfo.h"
1617

1718
using namespace llvm;
1819

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