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[RISCV] Expand constant multiplication for targets without M extension
1 parent fef1456 commit a9379d0

12 files changed

+1490
-699
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 109 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#include "RISCVSelectionDAGInfo.h"
2121
#include "RISCVSubtarget.h"
2222
#include "llvm/ADT/SmallSet.h"
23+
#include "llvm/ADT/SmallVector.h"
2324
#include "llvm/ADT/Statistic.h"
2425
#include "llvm/Analysis/MemoryLocation.h"
2526
#include "llvm/Analysis/ValueTracking.h"
@@ -15407,6 +15408,105 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
1540715408
return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
1540815409
}
1540915410

15411+
static SDValue expandMulToNAFSequence(SDNode *N, SelectionDAG &DAG,
15412+
const SDLoc &DL, uint64_t MulAmt) {
15413+
EVT VT = N->getValueType(0);
15414+
const uint64_t BitWidth = VT.getFixedSizeInBits();
15415+
15416+
// Find the Non-adjacent form of the multiplier.
15417+
llvm::SmallVector<std::pair<bool, uint64_t>> Sequence; // {isAdd, shamt}
15418+
for (uint64_t E = MulAmt, I = 0; E && I < BitWidth; ++I, E >>= 1) {
15419+
if (E & 1) {
15420+
bool IsAdd = (E & 3) == 1;
15421+
Sequence.push_back({IsAdd, I});
15422+
E -= IsAdd ? 1 : -1;
15423+
}
15424+
}
15425+
15426+
SDValue Result = DAG.getConstant(0, DL, N->getValueType(0));
15427+
SDValue N0 = N->getOperand(0);
15428+
15429+
for (const auto &Op : Sequence) {
15430+
SDValue ShiftVal;
15431+
if (Op.second > 0)
15432+
ShiftVal =
15433+
DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(Op.second, DL, VT));
15434+
else
15435+
ShiftVal = N0;
15436+
15437+
ISD::NodeType AddSubOp = Op.first ? ISD::ADD : ISD::SUB;
15438+
Result = DAG.getNode(AddSubOp, DL, VT, Result, ShiftVal);
15439+
}
15440+
return Result;
15441+
}
15442+
// Try to expand a multiply to a sequence of shifts and add/subs,
15443+
// for a machine without native mul instruction.
15444+
static SDValue expandMulToBasicOps(SDNode *N, SelectionDAG &DAG,
15445+
uint64_t MulAmt) {
15446+
EVT VT = N->getValueType(0);
15447+
const uint64_t BitWidth = VT.getFixedSizeInBits();
15448+
SDLoc DL(N);
15449+
15450+
if (MulAmt == 0)
15451+
return DAG.getConstant(0, DL, N->getValueType(0));
15452+
15453+
// Try to factorize into (2^N) * (2^M_1 +/- 1) * (2^M_2 +/- 1) * ...
15454+
uint64_t TrailingZeros = llvm::countr_zero(MulAmt);
15455+
uint64_t E = MulAmt >> TrailingZeros;
15456+
15457+
llvm::SmallVector<std::pair<bool, uint64_t>> Factors; // {is_2^M+1, M}
15458+
15459+
while (E > 1) {
15460+
bool Found = false;
15461+
for (int64_t I = BitWidth - 1; I >= 2; --I) {
15462+
uint64_t Factor = 1ULL << I;
15463+
15464+
if (E % (Factor + 1) == 0) {
15465+
Factors.push_back({true, I});
15466+
E /= Factor + 1;
15467+
Found = true;
15468+
break;
15469+
}
15470+
if (E % (Factor - 1) == 0) {
15471+
Factors.push_back({false, I});
15472+
E /= Factor - 1;
15473+
Found = true;
15474+
break;
15475+
}
15476+
}
15477+
if (!Found)
15478+
break;
15479+
}
15480+
15481+
SDValue Result;
15482+
SDValue N0 = N->getOperand(0);
15483+
15484+
bool UseFactorization = !Factors.empty() && (Factors.size() < 5);
15485+
15486+
if (UseFactorization) {
15487+
if (E == 1)
15488+
Result = N0;
15489+
else
15490+
Result = expandMulToNAFSequence(N, DAG, DL, E);
15491+
15492+
for (const auto &F : Factors) {
15493+
SDValue ShiftVal = DAG.getNode(ISD::SHL, DL, VT, Result,
15494+
DAG.getConstant(F.second, DL, VT));
15495+
15496+
ISD::NodeType AddSubOp = F.first ? ISD::ADD : ISD::SUB;
15497+
Result = DAG.getNode(AddSubOp, DL, N->getValueType(0), ShiftVal, Result);
15498+
}
15499+
15500+
if (TrailingZeros > 0)
15501+
Result = DAG.getNode(ISD::SHL, DL, VT, Result,
15502+
DAG.getConstant(TrailingZeros, DL, VT));
15503+
15504+
return Result;
15505+
}
15506+
15507+
return expandMulToNAFSequence(N, DAG, DL, MulAmt);
15508+
}
15509+
1541015510
// X * (2^N +/- 2^M) -> (add/sub (shl X, C1), (shl X, C2))
1541115511
static SDValue expandMulToAddOrSubOfShl(SDNode *N, SelectionDAG &DAG,
1541215512
uint64_t MulAmt) {
@@ -15442,20 +15542,23 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG,
1544215542
if (DAG.getMachineFunction().getFunction().hasMinSize())
1544315543
return SDValue();
1544415544

15445-
if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
15446-
return SDValue();
15447-
1544815545
if (VT != Subtarget.getXLenVT())
1544915546
return SDValue();
1545015547

15451-
const bool HasShlAdd =
15452-
Subtarget.hasStdExtZba() || Subtarget.hasVendorXTHeadBa();
15453-
1545415548
ConstantSDNode *CNode = dyn_cast<ConstantSDNode>(N->getOperand(1));
1545515549
if (!CNode)
1545615550
return SDValue();
1545715551
uint64_t MulAmt = CNode->getZExtValue();
1545815552

15553+
if (!Subtarget.hasStdExtM() && !Subtarget.hasStdExtZmmul())
15554+
return expandMulToBasicOps(N, DAG, MulAmt);
15555+
15556+
if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
15557+
return SDValue();
15558+
15559+
const bool HasShlAdd =
15560+
Subtarget.hasStdExtZba() || Subtarget.hasVendorXTHeadBa();
15561+
1545915562
// WARNING: The code below is knowingly incorrect with regards to undef semantics.
1546015563
// We're adding additional uses of X here, and in principle, we should be freezing
1546115564
// X before doing so. However, adding freeze here causes real regressions, and no

‎llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll

Lines changed: 42 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -262,20 +262,33 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
262262
; RV64I-NEXT: sext.w a1, a0
263263
; RV64I-NEXT: beqz a1, .LBB2_2
264264
; RV64I-NEXT: # %bb.1: # %cond.false
265-
; RV64I-NEXT: addi sp, sp, -16
266-
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
267-
; RV64I-NEXT: neg a1, a0
265+
; RV64I-NEXT: negw a1, a0
268266
; RV64I-NEXT: and a0, a0, a1
269-
; RV64I-NEXT: lui a1, 30667
270-
; RV64I-NEXT: addiw a1, a1, 1329
271-
; RV64I-NEXT: call __muldi3
267+
; RV64I-NEXT: slli a1, a0, 6
268+
; RV64I-NEXT: slli a2, a0, 8
269+
; RV64I-NEXT: slli a3, a0, 10
270+
; RV64I-NEXT: slli a4, a0, 12
271+
; RV64I-NEXT: add a1, a1, a2
272+
; RV64I-NEXT: slli a2, a0, 16
273+
; RV64I-NEXT: subw a3, a3, a4
274+
; RV64I-NEXT: slli a4, a0, 18
275+
; RV64I-NEXT: subw a2, a2, a4
276+
; RV64I-NEXT: slli a4, a0, 4
277+
; RV64I-NEXT: subw a4, a0, a4
278+
; RV64I-NEXT: add a1, a4, a1
279+
; RV64I-NEXT: slli a4, a0, 14
280+
; RV64I-NEXT: subw a3, a3, a4
281+
; RV64I-NEXT: slli a4, a0, 23
282+
; RV64I-NEXT: subw a2, a2, a4
283+
; RV64I-NEXT: slli a0, a0, 27
284+
; RV64I-NEXT: add a1, a1, a3
285+
; RV64I-NEXT: add a0, a2, a0
286+
; RV64I-NEXT: add a0, a1, a0
272287
; RV64I-NEXT: srliw a0, a0, 27
273288
; RV64I-NEXT: lui a1, %hi(.LCPI2_0)
274289
; RV64I-NEXT: addi a1, a1, %lo(.LCPI2_0)
275290
; RV64I-NEXT: add a0, a1, a0
276291
; RV64I-NEXT: lbu a0, 0(a0)
277-
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
278-
; RV64I-NEXT: addi sp, sp, 16
279292
; RV64I-NEXT: ret
280293
; RV64I-NEXT: .LBB2_2:
281294
; RV64I-NEXT: li a0, 32
@@ -730,20 +743,33 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
730743
;
731744
; RV64I-LABEL: test_cttz_i32_zero_undef:
732745
; RV64I: # %bb.0:
733-
; RV64I-NEXT: addi sp, sp, -16
734-
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
735-
; RV64I-NEXT: neg a1, a0
746+
; RV64I-NEXT: negw a1, a0
736747
; RV64I-NEXT: and a0, a0, a1
737-
; RV64I-NEXT: lui a1, 30667
738-
; RV64I-NEXT: addiw a1, a1, 1329
739-
; RV64I-NEXT: call __muldi3
748+
; RV64I-NEXT: slli a1, a0, 6
749+
; RV64I-NEXT: slli a2, a0, 8
750+
; RV64I-NEXT: slli a3, a0, 10
751+
; RV64I-NEXT: slli a4, a0, 12
752+
; RV64I-NEXT: add a1, a1, a2
753+
; RV64I-NEXT: slli a2, a0, 16
754+
; RV64I-NEXT: subw a3, a3, a4
755+
; RV64I-NEXT: slli a4, a0, 18
756+
; RV64I-NEXT: subw a2, a2, a4
757+
; RV64I-NEXT: slli a4, a0, 4
758+
; RV64I-NEXT: subw a4, a0, a4
759+
; RV64I-NEXT: add a1, a4, a1
760+
; RV64I-NEXT: slli a4, a0, 14
761+
; RV64I-NEXT: subw a3, a3, a4
762+
; RV64I-NEXT: slli a4, a0, 23
763+
; RV64I-NEXT: subw a2, a2, a4
764+
; RV64I-NEXT: slli a0, a0, 27
765+
; RV64I-NEXT: add a1, a1, a3
766+
; RV64I-NEXT: add a0, a2, a0
767+
; RV64I-NEXT: add a0, a1, a0
740768
; RV64I-NEXT: srliw a0, a0, 27
741769
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
742770
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0)
743771
; RV64I-NEXT: add a0, a1, a0
744772
; RV64I-NEXT: lbu a0, 0(a0)
745-
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
746-
; RV64I-NEXT: addi sp, sp, 16
747773
; RV64I-NEXT: ret
748774
;
749775
; RV32M-LABEL: test_cttz_i32_zero_undef:

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