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Add clarifying parenthesis around non-trivial conditions in ternary expressions. (#90391)
Fixes [#85868](#85868) Parenthesis are added as requested on ternary operators with non trivial conditions. I used this [precedence table](https://en.cppreference.com/w/cpp/language/operator_precedence) for reference, to make sure we get the expected behavior on each change.
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18 files changed

+94
-96
lines changed

18 files changed

+94
-96
lines changed

‎clang/lib/Basic/Targets/AMDGPU.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -232,7 +232,7 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple &Triple,
232232

233233
HasLegalHalfType = true;
234234
HasFloat16 = true;
235-
WavefrontSize = GPUFeatures & llvm::AMDGPU::FEATURE_WAVE32 ? 32 : 64;
235+
WavefrontSize = (GPUFeatures & llvm::AMDGPU::FEATURE_WAVE32) ? 32 : 64;
236236
AllowAMDGPUUnsafeFPAtomics = Opts.AllowAMDGPUUnsafeFPAtomics;
237237

238238
// Set pointer width and alignment for the generic address space.

‎compiler-rt/lib/xray/xray_utils.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ constexpr size_t gcd(size_t a, size_t b) {
6161
constexpr size_t lcm(size_t a, size_t b) { return a * b / gcd(a, b); }
6262

6363
constexpr size_t nearest_boundary(size_t number, size_t multiple) {
64-
return multiple * ((number / multiple) + (number % multiple ? 1 : 0));
64+
return multiple * ((number / multiple) + ((number % multiple) ? 1 : 0));
6565
}
6666

6767
constexpr size_t next_pow2_helper(size_t num, size_t acc) {

‎libc/src/__support/FPUtil/aarch64/FEnvImpl.h

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -53,19 +53,19 @@ struct FEnv {
5353
static constexpr uint32_t ExceptionControlFlagsBitPosition = 8;
5454

5555
LIBC_INLINE static uint32_t getStatusValueForExcept(int excepts) {
56-
return (excepts & FE_INVALID ? INVALID : 0) |
57-
(excepts & FE_DIVBYZERO ? DIVBYZERO : 0) |
58-
(excepts & FE_OVERFLOW ? OVERFLOW : 0) |
59-
(excepts & FE_UNDERFLOW ? UNDERFLOW : 0) |
60-
(excepts & FE_INEXACT ? INEXACT : 0);
56+
return ((excepts & FE_INVALID) ? INVALID : 0) |
57+
((excepts & FE_DIVBYZERO) ? DIVBYZERO : 0) |
58+
((excepts & FE_OVERFLOW) ? OVERFLOW : 0) |
59+
((excepts & FE_UNDERFLOW) ? UNDERFLOW : 0) |
60+
((excepts & FE_INEXACT) ? INEXACT : 0);
6161
}
6262

6363
LIBC_INLINE static int exceptionStatusToMacro(uint32_t status) {
64-
return (status & INVALID ? FE_INVALID : 0) |
65-
(status & DIVBYZERO ? FE_DIVBYZERO : 0) |
66-
(status & OVERFLOW ? FE_OVERFLOW : 0) |
67-
(status & UNDERFLOW ? FE_UNDERFLOW : 0) |
68-
(status & INEXACT ? FE_INEXACT : 0);
64+
return ((status & INVALID) ? FE_INVALID : 0) |
65+
((status & DIVBYZERO) ? FE_DIVBYZERO : 0) |
66+
((status & OVERFLOW) ? FE_OVERFLOW : 0) |
67+
((status & UNDERFLOW) ? FE_UNDERFLOW : 0) |
68+
((status & INEXACT) ? FE_INEXACT : 0);
6969
}
7070

7171
static uint32_t getControlWord() {

‎libc/src/__support/FPUtil/aarch64/fenv_darwin_impl.h

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -63,39 +63,39 @@ struct FEnv {
6363
// located in a different place from FE_FLUSHTOZERO status bit relative to
6464
// the other exceptions.
6565
LIBC_INLINE static uint32_t exception_value_from_status(int status) {
66-
return (status & FE_INVALID ? EX_INVALID : 0) |
67-
(status & FE_DIVBYZERO ? EX_DIVBYZERO : 0) |
68-
(status & FE_OVERFLOW ? EX_OVERFLOW : 0) |
69-
(status & FE_UNDERFLOW ? EX_UNDERFLOW : 0) |
70-
(status & FE_INEXACT ? EX_INEXACT : 0) |
71-
(status & FE_FLUSHTOZERO ? EX_FLUSHTOZERO : 0);
66+
return ((status & FE_INVALID) ? EX_INVALID : 0) |
67+
((status & FE_DIVBYZERO) ? EX_DIVBYZERO : 0) |
68+
((status & FE_OVERFLOW) ? EX_OVERFLOW : 0) |
69+
((status & FE_UNDERFLOW) ? EX_UNDERFLOW : 0) |
70+
((status & FE_INEXACT) ? EX_INEXACT : 0) |
71+
((status & FE_FLUSHTOZERO) ? EX_FLUSHTOZERO : 0);
7272
}
7373

7474
LIBC_INLINE static uint32_t exception_value_from_control(int control) {
75-
return (control & __fpcr_trap_invalid ? EX_INVALID : 0) |
76-
(control & __fpcr_trap_divbyzero ? EX_DIVBYZERO : 0) |
77-
(control & __fpcr_trap_overflow ? EX_OVERFLOW : 0) |
78-
(control & __fpcr_trap_underflow ? EX_UNDERFLOW : 0) |
79-
(control & __fpcr_trap_inexact ? EX_INEXACT : 0) |
80-
(control & __fpcr_flush_to_zero ? EX_FLUSHTOZERO : 0);
75+
return ((control & __fpcr_trap_invalid) ? EX_INVALID : 0) |
76+
((control & __fpcr_trap_divbyzero) ? EX_DIVBYZERO : 0) |
77+
((control & __fpcr_trap_overflow) ? EX_OVERFLOW : 0) |
78+
((control & __fpcr_trap_underflow) ? EX_UNDERFLOW : 0) |
79+
((control & __fpcr_trap_inexact) ? EX_INEXACT : 0) |
80+
((control & __fpcr_flush_to_zero) ? EX_FLUSHTOZERO : 0);
8181
}
8282

8383
LIBC_INLINE static int exception_value_to_status(uint32_t excepts) {
84-
return (excepts & EX_INVALID ? FE_INVALID : 0) |
85-
(excepts & EX_DIVBYZERO ? FE_DIVBYZERO : 0) |
86-
(excepts & EX_OVERFLOW ? FE_OVERFLOW : 0) |
87-
(excepts & EX_UNDERFLOW ? FE_UNDERFLOW : 0) |
88-
(excepts & EX_INEXACT ? FE_INEXACT : 0) |
89-
(excepts & EX_FLUSHTOZERO ? FE_FLUSHTOZERO : 0);
84+
return ((excepts & EX_INVALID) ? FE_INVALID : 0) |
85+
((excepts & EX_DIVBYZERO) ? FE_DIVBYZERO : 0) |
86+
((excepts & EX_OVERFLOW) ? FE_OVERFLOW : 0) |
87+
((excepts & EX_UNDERFLOW) ? FE_UNDERFLOW : 0) |
88+
((excepts & EX_INEXACT) ? FE_INEXACT : 0) |
89+
((excepts & EX_FLUSHTOZERO) ? FE_FLUSHTOZERO : 0);
9090
}
9191

9292
LIBC_INLINE static int exception_value_to_control(uint32_t excepts) {
93-
return (excepts & EX_INVALID ? __fpcr_trap_invalid : 0) |
94-
(excepts & EX_DIVBYZERO ? __fpcr_trap_divbyzero : 0) |
95-
(excepts & EX_OVERFLOW ? __fpcr_trap_overflow : 0) |
96-
(excepts & EX_UNDERFLOW ? __fpcr_trap_underflow : 0) |
97-
(excepts & EX_INEXACT ? __fpcr_trap_inexact : 0) |
98-
(excepts & EX_FLUSHTOZERO ? __fpcr_flush_to_zero : 0);
93+
return ((excepts & EX_INVALID) ? __fpcr_trap_invalid : 0) |
94+
((excepts & EX_DIVBYZERO) ? __fpcr_trap_divbyzero : 0) |
95+
((excepts & EX_OVERFLOW) ? __fpcr_trap_overflow : 0) |
96+
((excepts & EX_UNDERFLOW) ? __fpcr_trap_underflow : 0) |
97+
((excepts & EX_INEXACT) ? __fpcr_trap_inexact : 0) |
98+
((excepts & EX_FLUSHTOZERO) ? __fpcr_flush_to_zero : 0);
9999
}
100100

101101
LIBC_INLINE static uint32_t get_control_word() { return __arm_rsr("fpcr"); }

‎libc/src/__support/FPUtil/arm/FEnvImpl.h

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -50,35 +50,35 @@ struct FEnv {
5050
}
5151

5252
LIBC_INLINE static int exception_enable_bits_to_macro(uint32_t status) {
53-
return (status & INVALID_ENABLE ? FE_INVALID : 0) |
54-
(status & DIVBYZERO_ENABLE ? FE_DIVBYZERO : 0) |
55-
(status & OVERFLOW_ENABLE ? FE_OVERFLOW : 0) |
56-
(status & UNDERFLOW_ENABLE ? FE_UNDERFLOW : 0) |
57-
(status & INEXACT_ENABLE ? FE_INEXACT : 0);
53+
return ((status & INVALID_ENABLE) ? FE_INVALID : 0) |
54+
((status & DIVBYZERO_ENABLE) ? FE_DIVBYZERO : 0) |
55+
((status & OVERFLOW_ENABLE) ? FE_OVERFLOW : 0) |
56+
((status & UNDERFLOW_ENABLE) ? FE_UNDERFLOW : 0) |
57+
((status & INEXACT_ENABLE) ? FE_INEXACT : 0);
5858
}
5959

6060
LIBC_INLINE static uint32_t exception_macro_to_enable_bits(int except) {
61-
return (except & FE_INVALID ? INVALID_ENABLE : 0) |
62-
(except & FE_DIVBYZERO ? DIVBYZERO_ENABLE : 0) |
63-
(except & FE_OVERFLOW ? OVERFLOW_ENABLE : 0) |
64-
(except & FE_UNDERFLOW ? UNDERFLOW_ENABLE : 0) |
65-
(except & FE_INEXACT ? INEXACT_ENABLE : 0);
61+
return ((except & FE_INVALID) ? INVALID_ENABLE : 0) |
62+
((except & FE_DIVBYZERO) ? DIVBYZERO_ENABLE : 0) |
63+
((except & FE_OVERFLOW) ? OVERFLOW_ENABLE : 0) |
64+
((except & FE_UNDERFLOW) ? UNDERFLOW_ENABLE : 0) |
65+
((except & FE_INEXACT) ? INEXACT_ENABLE : 0);
6666
}
6767

6868
LIBC_INLINE static uint32_t exception_macro_to_status_bits(int except) {
69-
return (except & FE_INVALID ? INVALID_STATUS : 0) |
70-
(except & FE_DIVBYZERO ? DIVBYZERO_STATUS : 0) |
71-
(except & FE_OVERFLOW ? OVERFLOW_STATUS : 0) |
72-
(except & FE_UNDERFLOW ? UNDERFLOW_STATUS : 0) |
73-
(except & FE_INEXACT ? INEXACT_STATUS : 0);
69+
return ((except & FE_INVALID) ? INVALID_STATUS : 0) |
70+
((except & FE_DIVBYZERO) ? DIVBYZERO_STATUS : 0) |
71+
((except & FE_OVERFLOW) ? OVERFLOW_STATUS : 0) |
72+
((except & FE_UNDERFLOW) ? UNDERFLOW_STATUS : 0) |
73+
((except & FE_INEXACT) ? INEXACT_STATUS : 0);
7474
}
7575

7676
LIBC_INLINE static uint32_t exception_status_bits_to_macro(int status) {
77-
return (status & INVALID_STATUS ? FE_INVALID : 0) |
78-
(status & DIVBYZERO_STATUS ? FE_DIVBYZERO : 0) |
79-
(status & OVERFLOW_STATUS ? FE_OVERFLOW : 0) |
80-
(status & UNDERFLOW_STATUS ? FE_UNDERFLOW : 0) |
81-
(status & INEXACT_STATUS ? FE_INEXACT : 0);
77+
return ((status & INVALID_STATUS) ? FE_INVALID : 0) |
78+
((status & DIVBYZERO_STATUS) ? FE_DIVBYZERO : 0) |
79+
((status & OVERFLOW_STATUS) ? FE_OVERFLOW : 0) |
80+
((status & UNDERFLOW_STATUS) ? FE_UNDERFLOW : 0) |
81+
((status & INEXACT_STATUS) ? FE_INEXACT : 0);
8282
}
8383
};
8484

‎libc/src/__support/FPUtil/riscv/FEnvImpl.h

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -65,19 +65,19 @@ struct FEnv {
6565
}
6666

6767
LIBC_INLINE static int exception_bits_to_macro(uint32_t status) {
68-
return (status & INVALID ? FE_INVALID : 0) |
69-
(status & DIVBYZERO ? FE_DIVBYZERO : 0) |
70-
(status & OVERFLOW ? FE_OVERFLOW : 0) |
71-
(status & UNDERFLOW ? FE_UNDERFLOW : 0) |
72-
(status & INEXACT ? FE_INEXACT : 0);
68+
return ((status & INVALID) ? FE_INVALID : 0) |
69+
((status & DIVBYZERO) ? FE_DIVBYZERO : 0) |
70+
((status & OVERFLOW) ? FE_OVERFLOW : 0) |
71+
((status & UNDERFLOW) ? FE_UNDERFLOW : 0) |
72+
((status & INEXACT) ? FE_INEXACT : 0);
7373
}
7474

7575
LIBC_INLINE static uint32_t exception_macro_to_bits(int except) {
76-
return (except & FE_INVALID ? INVALID : 0) |
77-
(except & FE_DIVBYZERO ? DIVBYZERO : 0) |
78-
(except & FE_OVERFLOW ? OVERFLOW : 0) |
79-
(except & FE_UNDERFLOW ? UNDERFLOW : 0) |
80-
(except & FE_INEXACT ? INEXACT : 0);
76+
return ((except & FE_INVALID) ? INVALID : 0) |
77+
((except & FE_DIVBYZERO) ? DIVBYZERO : 0) |
78+
((except & FE_OVERFLOW) ? OVERFLOW : 0) |
79+
((except & FE_UNDERFLOW) ? UNDERFLOW : 0) |
80+
((except & FE_INEXACT) ? INEXACT : 0);
8181
}
8282
};
8383

‎libc/src/__support/FPUtil/x86_64/FEnvImpl.h

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -72,25 +72,25 @@ static constexpr uint16_t MXCSR_EXCEPTION_CONTOL_BIT_POISTION = 7;
7272
LIBC_INLINE uint16_t get_status_value_for_except(int excepts) {
7373
// We will make use of the fact that exception control bits are single
7474
// bit flags in the control registers.
75-
return (excepts & FE_INVALID ? ExceptionFlags::INVALID_F : 0) |
75+
return ((excepts & FE_INVALID) ? ExceptionFlags::INVALID_F : 0) |
7676
#ifdef __FE_DENORM
77-
(excepts & __FE_DENORM ? ExceptionFlags::DENORMAL_F : 0) |
77+
((excepts & __FE_DENORM) ? ExceptionFlags::DENORMAL_F : 0) |
7878
#endif // __FE_DENORM
79-
(excepts & FE_DIVBYZERO ? ExceptionFlags::DIV_BY_ZERO_F : 0) |
80-
(excepts & FE_OVERFLOW ? ExceptionFlags::OVERFLOW_F : 0) |
81-
(excepts & FE_UNDERFLOW ? ExceptionFlags::UNDERFLOW_F : 0) |
82-
(excepts & FE_INEXACT ? ExceptionFlags::INEXACT_F : 0);
79+
((excepts & FE_DIVBYZERO) ? ExceptionFlags::DIV_BY_ZERO_F : 0) |
80+
((excepts & FE_OVERFLOW) ? ExceptionFlags::OVERFLOW_F : 0) |
81+
((excepts & FE_UNDERFLOW) ? ExceptionFlags::UNDERFLOW_F : 0) |
82+
((excepts & FE_INEXACT) ? ExceptionFlags::INEXACT_F : 0);
8383
}
8484

8585
LIBC_INLINE int exception_status_to_macro(uint16_t status) {
86-
return (status & ExceptionFlags::INVALID_F ? FE_INVALID : 0) |
86+
return ((status & ExceptionFlags::INVALID_F) ? FE_INVALID : 0) |
8787
#ifdef __FE_DENORM
88-
(status & ExceptionFlags::DENORMAL_F ? __FE_DENORM : 0) |
88+
((status & ExceptionFlags::DENORMAL_F) ? __FE_DENORM : 0) |
8989
#endif // __FE_DENORM
90-
(status & ExceptionFlags::DIV_BY_ZERO_F ? FE_DIVBYZERO : 0) |
91-
(status & ExceptionFlags::OVERFLOW_F ? FE_OVERFLOW : 0) |
92-
(status & ExceptionFlags::UNDERFLOW_F ? FE_UNDERFLOW : 0) |
93-
(status & ExceptionFlags::INEXACT_F ? FE_INEXACT : 0);
90+
((status & ExceptionFlags::DIV_BY_ZERO_F) ? FE_DIVBYZERO : 0) |
91+
((status & ExceptionFlags::OVERFLOW_F) ? FE_OVERFLOW : 0) |
92+
((status & ExceptionFlags::UNDERFLOW_F) ? FE_UNDERFLOW : 0) |
93+
((status & ExceptionFlags::INEXACT_F) ? FE_INEXACT : 0);
9494
}
9595

9696
struct X87StateDescriptor {

‎libclc/generic/lib/math/log_base.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -289,7 +289,7 @@ log(double x)
289289
double ret = is_near ? ret_near : ret_far;
290290

291291
ret = isinf(x) ? as_double(PINFBITPATT_DP64) : ret;
292-
ret = isnan(x) | (x < 0.0) ? as_double(QNANBITPATT_DP64) : ret;
292+
ret = (isnan(x) | (x < 0.0)) ? as_double(QNANBITPATT_DP64) : ret;
293293
ret = x == 0.0 ? as_double(NINFBITPATT_DP64) : ret;
294294
return ret;
295295
}

‎libcxxabi/src/cxa_personality.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -717,9 +717,7 @@ static void scan_eh_tab(scan_results &results, _Unwind_Action actions,
717717
if (actionEntry == 0)
718718
{
719719
// Found a cleanup
720-
results.reason = actions & _UA_SEARCH_PHASE
721-
? _URC_CONTINUE_UNWIND
722-
: _URC_HANDLER_FOUND;
720+
results.reason = (actions & _UA_SEARCH_PHASE) ? _URC_CONTINUE_UNWIND : _URC_HANDLER_FOUND;
723721
return;
724722
}
725723
// Convert 1-based byte offset into

‎lld/ELF/LinkerScript.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -801,7 +801,7 @@ static OutputDesc *addInputSec(StringMap<TinyPtrVector<OutputSection *>> &map,
801801
auto *firstIsec = cast<InputSectionBase>(
802802
cast<InputSectionDescription>(sec->commands[0])->sectionBases[0]);
803803
OutputSection *firstIsecOut =
804-
firstIsec->flags & SHF_LINK_ORDER
804+
(firstIsec->flags & SHF_LINK_ORDER)
805805
? firstIsec->getLinkOrderDep()->getOutputSection()
806806
: nullptr;
807807
if (firstIsecOut != isec->getLinkOrderDep()->getOutputSection())

‎lldb/tools/debugserver/source/MacOSX/MachException.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -247,7 +247,7 @@ kern_return_t MachException::Message::Receive(mach_port_t port,
247247
DNBError err;
248248
const bool log_exceptions = DNBLogCheckLogBit(LOG_EXCEPTIONS);
249249
mach_msg_timeout_t mach_msg_timeout =
250-
options & MACH_RCV_TIMEOUT ? timeout : 0;
250+
(options & MACH_RCV_TIMEOUT) ? timeout : 0;
251251
if (log_exceptions && ((options & MACH_RCV_TIMEOUT) == 0)) {
252252
// Dump this log message if we have no timeout in case it never returns
253253
DNBLogThreaded("::mach_msg ( msg->{bits = %#x, size = %u remote_port = "

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3910,8 +3910,8 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
39103910
const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
39113911
AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
39123912
int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
3913-
int RSrcOpName = Desc.TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc
3914-
: AMDGPU::OpName::rsrc;
3913+
int RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc
3914+
: AMDGPU::OpName::rsrc;
39153915
int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RSrcOpName);
39163916
int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);
39173917
int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16);

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -921,8 +921,8 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
921921
AMDGPU::OpName::vdata);
922922
int VAddr0Idx =
923923
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
924-
int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc
925-
: AMDGPU::OpName::rsrc;
924+
int RsrcOpName = (TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc
925+
: AMDGPU::OpName::rsrc;
926926
int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName);
927927
int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
928928
AMDGPU::OpName::dmask);

‎llvm/lib/Target/AVR/AVRAsmPrinter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -134,8 +134,8 @@ bool AVRAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
134134
Reg = MI->getOperand(OpNum + RegIdx).getReg();
135135

136136
if (BytesPerReg == 2) {
137-
Reg = TRI.getSubReg(Reg,
138-
ByteNumber % BytesPerReg ? AVR::sub_hi : AVR::sub_lo);
137+
Reg = TRI.getSubReg(Reg, (ByteNumber % BytesPerReg) ? AVR::sub_hi
138+
: AVR::sub_lo);
139139
}
140140

141141
O << AVRInstPrinter::getPrettyRegisterName(Reg, MRI);

‎llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2146,8 +2146,8 @@ prepareCompareSwapOperands(MachineBasicBlock::iterator const MBBI) const {
21462146

21472147
unsigned SystemZ::reverseCCMask(unsigned CCMask) {
21482148
return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
2149-
(CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
2150-
(CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
2149+
((CCMask & SystemZ::CCMASK_CMP_GT) ? SystemZ::CCMASK_CMP_LT : 0) |
2150+
((CCMask & SystemZ::CCMASK_CMP_LT) ? SystemZ::CCMASK_CMP_GT : 0) |
21512151
(CCMask & SystemZ::CCMASK_CMP_UO));
21522152
}
21532153

‎llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3802,7 +3802,7 @@ bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
38023802
// VFMULCPHZrr Dest, Src1, Src2
38033803
// VFMULCPHZrrk Dest, Dest, Mask, Src1, Src2
38043804
// VFMULCPHZrrkz Dest, Mask, Src1, Src2
3805-
for (unsigned i = TSFlags & X86II::EVEX_K ? 2 : 1;
3805+
for (unsigned i = ((TSFlags & X86II::EVEX_K) ? 2 : 1);
38063806
i < Inst.getNumOperands(); i++)
38073807
if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
38083808
return Warning(Ops[0]->getStartLoc(), "Destination register should be "

‎llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -980,7 +980,7 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
980980
break;
981981
case X86II::VEX:
982982
// VEX can be 2 byte or 3 byte, not determined yet if not explicit
983-
Prefix.setLowerBound(MI.getFlags() & X86::IP_USE_VEX3 ? VEX3 : VEX2);
983+
Prefix.setLowerBound((MI.getFlags() & X86::IP_USE_VEX3) ? VEX3 : VEX2);
984984
break;
985985
case X86II::EVEX:
986986
Prefix.setLowerBound(EVEX);

‎mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -182,9 +182,9 @@ class TransposeConvStridedConverter
182182
// Pad the weight so that it is modulo of the striding.
183183
llvm::SmallVector<int32_t, 8> weightPadding = {0, 0, 0, 0, 0, 0, 0, 0};
184184
weightPadding[3] =
185-
weightHeight % stride[0] ? stride[0] - weightHeight % stride[0] : 0;
185+
(weightHeight % stride[0]) ? (stride[0] - weightHeight % stride[0]) : 0;
186186
weightPadding[5] =
187-
weightWidth % stride[1] ? stride[1] - weightWidth % stride[1] : 0;
187+
(weightWidth % stride[1]) ? (stride[1] - weightWidth % stride[1]) : 0;
188188
DenseElementsAttr weightPaddingAttr = DenseIntElementsAttr::get(
189189
RankedTensorType::get({4, 2}, rewriter.getI32Type()), weightPadding);
190190
Value weightPaddingVal = createOpAndInfer<tosa::ConstOp>(

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