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[WebAssembly][NFC] Remove duplicate SIMD instructions and predicates
Summary: Instead of having different v128.load and v128.store instructions for each MVT, just have one of each that is reused in all the patterns. Also removes the HasSIMD128 predicate where accompanied by HasUnimplementedSIMD128, since the latter implies the former. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67930 llvm-svn: 372792
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-59
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2 files changed

+32
-59
lines changed

‎llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

Lines changed: 4 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -333,30 +333,10 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
333333
case WebAssembly::LOAD_SPLAT_v64x2:
334334
case WebAssembly::LOAD_SPLAT_v64x2_S:
335335
return 3;
336-
case WebAssembly::LOAD_v16i8:
337-
case WebAssembly::LOAD_v16i8_S:
338-
case WebAssembly::LOAD_v8i16:
339-
case WebAssembly::LOAD_v8i16_S:
340-
case WebAssembly::LOAD_v4i32:
341-
case WebAssembly::LOAD_v4i32_S:
342-
case WebAssembly::LOAD_v2i64:
343-
case WebAssembly::LOAD_v2i64_S:
344-
case WebAssembly::LOAD_v4f32:
345-
case WebAssembly::LOAD_v4f32_S:
346-
case WebAssembly::LOAD_v2f64:
347-
case WebAssembly::LOAD_v2f64_S:
348-
case WebAssembly::STORE_v16i8:
349-
case WebAssembly::STORE_v16i8_S:
350-
case WebAssembly::STORE_v8i16:
351-
case WebAssembly::STORE_v8i16_S:
352-
case WebAssembly::STORE_v4i32:
353-
case WebAssembly::STORE_v4i32_S:
354-
case WebAssembly::STORE_v2i64:
355-
case WebAssembly::STORE_v2i64_S:
356-
case WebAssembly::STORE_v4f32:
357-
case WebAssembly::STORE_v4f32_S:
358-
case WebAssembly::STORE_v2f64:
359-
case WebAssembly::STORE_v2f64_S:
336+
case WebAssembly::LOAD_V128:
337+
case WebAssembly::LOAD_V128_S:
338+
case WebAssembly::STORE_V128:
339+
case WebAssembly::STORE_V128_S:
360340
return 4;
361341
default:
362342
return -1;

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Lines changed: 28 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -40,24 +40,20 @@ def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
4040
//===----------------------------------------------------------------------===//
4141

4242
// Load: v128.load
43-
multiclass SIMDLoad<ValueType vec_t> {
44-
let mayLoad = 1, UseNamedOperandTable = 1 in
45-
defm LOAD_#vec_t :
46-
SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
47-
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
48-
"v128.load\t$dst, ${off}(${addr})$p2align",
49-
"v128.load\t$off$p2align", 0>;
50-
}
51-
52-
foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
53-
defm "" : SIMDLoad<vec_t>;
43+
let mayLoad = 1, UseNamedOperandTable = 1 in
44+
defm LOAD_V128 :
45+
SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
46+
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
47+
"v128.load\t$dst, ${off}(${addr})$p2align",
48+
"v128.load\t$off$p2align", 0>;
5449

5550
// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
56-
def : LoadPatNoOffset<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
57-
def : LoadPatImmOff<vec_t, load, regPlusImm, !cast<NI>("LOAD_"#vec_t)>;
58-
def : LoadPatImmOff<vec_t, load, or_is_add, !cast<NI>("LOAD_"#vec_t)>;
59-
def : LoadPatOffsetOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
60-
def : LoadPatGlobalAddrOffOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
51+
foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
52+
def : LoadPatNoOffset<vec_t, load, LOAD_V128>;
53+
def : LoadPatImmOff<vec_t, load, regPlusImm, LOAD_V128>;
54+
def : LoadPatImmOff<vec_t, load, or_is_add, LOAD_V128>;
55+
def : LoadPatOffsetOnly<vec_t, load, LOAD_V128>;
56+
def : LoadPatGlobalAddrOffOnly<vec_t, load, LOAD_V128>;
6157
}
6258

6359
// vNxM.load_splat
@@ -109,24 +105,20 @@ def : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]),
109105
}
110106

111107
// Store: v128.store
112-
multiclass SIMDStore<ValueType vec_t> {
113-
let mayStore = 1, UseNamedOperandTable = 1 in
114-
defm STORE_#vec_t :
115-
SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec),
116-
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
117-
"v128.store\t${off}(${addr})$p2align, $vec",
118-
"v128.store\t$off$p2align", 1>;
119-
}
108+
let mayStore = 1, UseNamedOperandTable = 1 in
109+
defm STORE_V128 :
110+
SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec),
111+
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
112+
"v128.store\t${off}(${addr})$p2align, $vec",
113+
"v128.store\t$off$p2align", 1>;
120114

121115
foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
122-
defm "" : SIMDStore<vec_t>;
123-
124116
// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
125-
def : StorePatNoOffset<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
126-
def : StorePatImmOff<vec_t, store, regPlusImm, !cast<NI>("STORE_"#vec_t)>;
127-
def : StorePatImmOff<vec_t, store, or_is_add, !cast<NI>("STORE_"#vec_t)>;
128-
def : StorePatOffsetOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
129-
def : StorePatGlobalAddrOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
117+
def : StorePatNoOffset<vec_t, store, STORE_V128>;
118+
def : StorePatImmOff<vec_t, store, regPlusImm, STORE_V128>;
119+
def : StorePatImmOff<vec_t, store, or_is_add, STORE_V128>;
120+
def : StorePatOffsetOnly<vec_t, store, STORE_V128>;
121+
def : StorePatGlobalAddrOffOnly<vec_t, store, STORE_V128>;
130122
}
131123

132124
//===----------------------------------------------------------------------===//
@@ -136,7 +128,7 @@ def : StorePatGlobalAddrOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
136128
// Constant: v128.const
137129
multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
138130
let isMoveImm = 1, isReMaterializable = 1,
139-
Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
131+
Predicates = [HasUnimplementedSIMD128] in
140132
defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
141133
[(set V128:$dst, (vec_t pat))],
142134
"v128.const\t$dst, "#args,
@@ -332,7 +324,7 @@ multiclass ExtractLaneExtended<string sign, bits<32> baseInst> {
332324
}
333325

334326
defm "" : ExtractLaneExtended<"_s", 5>;
335-
let Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
327+
let Predicates = [HasUnimplementedSIMD128] in
336328
defm "" : ExtractLaneExtended<"_u", 6>;
337329
defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>;
338330
defm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 16>;
@@ -701,7 +693,7 @@ defm ABS : SIMDUnaryFP<fabs, "abs", 149>;
701693
defm NEG : SIMDUnaryFP<fneg, "neg", 150>;
702694

703695
// Square root: sqrt
704-
let Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
696+
let Predicates = [HasUnimplementedSIMD128] in
705697
defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 151>;
706698

707699
//===----------------------------------------------------------------------===//
@@ -725,7 +717,7 @@ let isCommutable = 1 in
725717
defm MUL : SIMDBinaryFP<fmul, "mul", 156>;
726718

727719
// Division: div
728-
let Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
720+
let Predicates = [HasUnimplementedSIMD128] in
729721
defm DIV : SIMDBinaryFP<fdiv, "div", 157>;
730722

731723
// NaN-propagating minimum: min
@@ -818,6 +810,7 @@ def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;
818810
//===----------------------------------------------------------------------===//
819811
// Quasi-Fused Multiply- Add and Subtract (QFMA/QFMS)
820812
//===----------------------------------------------------------------------===//
813+
821814
multiclass SIMDQFM<ValueType vec_t, string vec, bits<32> baseInst> {
822815
defm QFMA_#vec_t :
823816
SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c),

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