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Cleanup of the two test cases.
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llvm/test/CodeGen/PowerPC/subreg-coalescer.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
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# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s \
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# RUN: -verify-coalescing --run-pass=register-coalescer -o - | FileCheck %s
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# Check that the register coalescer correctly handles merging live ranges over

llvm/test/CodeGen/X86/subreg-fail.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple x86_64-unknown-unknown -x mir < %s \
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# RUN: -verify-coalescing -enable-subreg-liveness=true \
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# RUN: llc -mtriple x86_64-unknown-unknown %s \
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# RUN: -verify-coalescing -enable-subreg-liveness \
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# RUN: --run-pass=register-coalescer -o - | FileCheck %s
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# Check that the register coalescer correctly handles merging live ranges over

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