Skip to content

Commit a9e05a3

Browse files
topperctopperc
committed
[ARM] Use MCRegister for ARMTargetStreamer::emitRegSave. NFC
1 parent f427028 commit a9e05a3

File tree

5 files changed

+25
-25
lines changed

5 files changed

+25
-25
lines changed

‎llvm/include/llvm/MC/MCStreamer.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ class ARMTargetStreamer : public MCTargetStreamer {
148148
int64_t Offset = 0);
149149
virtual void emitMovSP(unsigned Reg, int64_t Offset = 0);
150150
virtual void emitPad(int64_t Offset);
151-
virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
151+
virtual void emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
152152
bool isVector);
153153
virtual void emitUnwindRaw(int64_t StackOffset,
154154
const SmallVectorImpl<uint8_t> &Opcodes);

‎llvm/lib/Target/ARM/ARMAsmPrinter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1219,7 +1219,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
12191219
assert(DstReg == ARM::SP &&
12201220
"Only stack pointer as a destination reg is supported");
12211221

1222-
SmallVector<unsigned, 4> RegList;
1222+
SmallVector<MCRegister, 4> RegList;
12231223
// Skip src & dst reg, and pred ops.
12241224
unsigned StartOp = 2 + 2;
12251225
// Use all the operands.

‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -808,7 +808,7 @@ class ARMOperand : public MCParsedAsmOperand {
808808
} Kind;
809809

810810
SMLoc StartLoc, EndLoc, AlignmentLoc;
811-
SmallVector<unsigned, 8> Registers;
811+
SmallVector<MCRegister, 8> Registers;
812812

813813
ARMAsmParser *Parser;
814814

@@ -1005,7 +1005,7 @@ class ARMOperand : public MCParsedAsmOperand {
10051005
return Reg.RegNum;
10061006
}
10071007

1008-
const SmallVectorImpl<unsigned> &getRegList() const {
1008+
const SmallVectorImpl<MCRegister> &getRegList() const {
10091009
assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
10101010
Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||
10111011
Kind == k_FPSRegisterListWithVPR ||
@@ -2630,15 +2630,15 @@ class ARMOperand : public MCParsedAsmOperand {
26302630

26312631
void addRegListOperands(MCInst &Inst, unsigned N) const {
26322632
assert(N == 1 && "Invalid number of operands!");
2633-
const SmallVectorImpl<unsigned> &RegList = getRegList();
2634-
for (unsigned Reg : RegList)
2633+
const SmallVectorImpl<MCRegister> &RegList = getRegList();
2634+
for (MCRegister Reg : RegList)
26352635
Inst.addOperand(MCOperand::createReg(Reg));
26362636
}
26372637

26382638
void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
26392639
assert(N == 1 && "Invalid number of operands!");
2640-
const SmallVectorImpl<unsigned> &RegList = getRegList();
2641-
for (unsigned Reg : RegList)
2640+
const SmallVectorImpl<MCRegister> &RegList = getRegList();
2641+
for (MCRegister Reg : RegList)
26422642
Inst.addOperand(MCOperand::createReg(Reg));
26432643
}
26442644

@@ -4103,7 +4103,7 @@ void ARMOperand::print(raw_ostream &OS) const {
41034103
case k_FPDRegisterListWithVPR: {
41044104
OS << "<register_list ";
41054105

4106-
const SmallVectorImpl<unsigned> &RegList = getRegList();
4106+
const SmallVectorImpl<MCRegister> &RegList = getRegList();
41074107
for (auto I = RegList.begin(), E = RegList.end(); I != E;) {
41084108
OS << RegName(*I);
41094109
if (++I < E) OS << ", ";
@@ -12519,7 +12519,7 @@ bool ARMAsmParser::parseDirectiveSEHSaveRegs(SMLoc L, bool Wide) {
1251912519
ARMOperand &Op = (ARMOperand &)*Operands[0];
1252012520
if (!Op.isRegList())
1252112521
return Error(L, ".seh_save_regs{_w} expects GPR registers");
12522-
const SmallVectorImpl<unsigned> &RegList = Op.getRegList();
12522+
const SmallVectorImpl<MCRegister> &RegList = Op.getRegList();
1252312523
uint32_t Mask = 0;
1252412524
for (size_t i = 0; i < RegList.size(); ++i) {
1252512525
unsigned Reg = MRI->getEncodingValue(RegList[i]);
@@ -12561,7 +12561,7 @@ bool ARMAsmParser::parseDirectiveSEHSaveFRegs(SMLoc L) {
1256112561
ARMOperand &Op = (ARMOperand &)*Operands[0];
1256212562
if (!Op.isDPRRegList())
1256312563
return Error(L, ".seh_save_fregs expects DPR registers");
12564-
const SmallVectorImpl<unsigned> &RegList = Op.getRegList();
12564+
const SmallVectorImpl<MCRegister> &RegList = Op.getRegList();
1256512565
uint32_t Mask = 0;
1256612566
for (size_t i = 0; i < RegList.size(); ++i) {
1256712567
unsigned Reg = MRI->getEncodingValue(RegList[i]);

‎llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ class ARMTargetAsmStreamer : public ARMTargetStreamer {
8383
void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0) override;
8484
void emitMovSP(unsigned Reg, int64_t Offset = 0) override;
8585
void emitPad(int64_t Offset) override;
86-
void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
86+
void emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
8787
bool isVector) override;
8888
void emitUnwindRaw(int64_t Offset,
8989
const SmallVectorImpl<uint8_t> &Opcodes) override;
@@ -165,8 +165,8 @@ void ARMTargetAsmStreamer::emitPad(int64_t Offset) {
165165
OS << "\t.pad\t#" << Offset << '\n';
166166
}
167167

168-
void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
169-
bool isVector) {
168+
void ARMTargetAsmStreamer::emitRegSave(
169+
const SmallVectorImpl<MCRegister> &RegList, bool isVector) {
170170
assert(RegList.size() && "RegList should not be empty");
171171
if (isVector)
172172
OS << "\t.vsave\t{";
@@ -404,7 +404,7 @@ class ARMTargetELFStreamer : public ARMTargetStreamer {
404404
void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0) override;
405405
void emitMovSP(unsigned Reg, int64_t Offset = 0) override;
406406
void emitPad(int64_t Offset) override;
407-
void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
407+
void emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
408408
bool isVector) override;
409409
void emitUnwindRaw(int64_t Offset,
410410
const SmallVectorImpl<uint8_t> &Opcodes) override;
@@ -472,7 +472,7 @@ class ARMELFStreamer : public MCELFStreamer {
472472
void emitSetFP(unsigned NewFpReg, unsigned NewSpReg, int64_t Offset = 0);
473473
void emitMovSP(unsigned Reg, int64_t Offset = 0);
474474
void emitPad(int64_t Offset);
475-
void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
475+
void emitRegSave(const SmallVectorImpl<MCRegister> &RegList, bool isVector);
476476
void emitUnwindRaw(int64_t Offset, const SmallVectorImpl<uint8_t> &Opcodes);
477477
void emitFill(const MCExpr &NumBytes, uint64_t FillValue,
478478
SMLoc Loc) override {
@@ -766,8 +766,8 @@ void ARMTargetELFStreamer::emitPad(int64_t Offset) {
766766
getStreamer().emitPad(Offset);
767767
}
768768

769-
void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
770-
bool isVector) {
769+
void ARMTargetELFStreamer::emitRegSave(
770+
const SmallVectorImpl<MCRegister> &RegList, bool isVector) {
771771
getStreamer().emitRegSave(RegList, isVector);
772772
}
773773

@@ -1412,17 +1412,17 @@ void ARMELFStreamer::emitPad(int64_t Offset) {
14121412

14131413
static std::pair<unsigned, unsigned>
14141414
collectHWRegs(const MCRegisterInfo &MRI, unsigned Idx,
1415-
const SmallVectorImpl<unsigned> &RegList, bool IsVector,
1415+
const SmallVectorImpl<MCRegister> &RegList, bool IsVector,
14161416
uint32_t &Mask_) {
14171417
uint32_t Mask = 0;
14181418
unsigned Count = 0;
14191419
while (Idx > 0) {
1420-
unsigned Reg = RegList[Idx - 1];
1420+
MCRegister Reg = RegList[Idx - 1];
14211421
if (Reg == ARM::RA_AUTH_CODE)
14221422
break;
1423-
Reg = MRI.getEncodingValue(Reg);
1424-
assert(Reg < (IsVector ? 32U : 16U) && "Register out of range");
1425-
unsigned Bit = (1u << Reg);
1423+
unsigned RegEnc = MRI.getEncodingValue(Reg);
1424+
assert(RegEnc < (IsVector ? 32U : 16U) && "Register out of range");
1425+
unsigned Bit = (1u << RegEnc);
14261426
if ((Mask & Bit) == 0) {
14271427
Mask |= Bit;
14281428
++Count;
@@ -1434,7 +1434,7 @@ collectHWRegs(const MCRegisterInfo &MRI, unsigned Idx,
14341434
return {Idx, Count};
14351435
}
14361436

1437-
void ARMELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
1437+
void ARMELFStreamer::emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
14381438
bool IsVector) {
14391439
uint32_t Mask;
14401440
unsigned Idx, Count;

‎llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@ void ARMTargetStreamer::emitSetFP(unsigned FpReg, unsigned SpReg,
9696
int64_t Offset) {}
9797
void ARMTargetStreamer::emitMovSP(unsigned Reg, int64_t Offset) {}
9898
void ARMTargetStreamer::emitPad(int64_t Offset) {}
99-
void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
99+
void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
100100
bool isVector) {}
101101
void ARMTargetStreamer::emitUnwindRaw(int64_t StackOffset,
102102
const SmallVectorImpl<uint8_t> &Opcodes) {

0 commit comments

Comments
 (0)