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kazutakahiratakazutakahirata
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[llvm] Remove unused local variables (NFC) (#138478)
1 parent 9a7e307 commit aa15596

18 files changed

+0
-31
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12356,7 +12356,6 @@ SDValue DAGCombiner::visitMSTORE(SDNode *N) {
1235612356
SDValue Chain = MST->getChain();
1235712357
SDValue Value = MST->getValue();
1235812358
SDValue Ptr = MST->getBasePtr();
12359-
SDLoc DL(N);
1236012359

1236112360
// Zap masked stores with a zero mask.
1236212361
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode()))
@@ -12559,7 +12558,6 @@ SDValue DAGCombiner::visitMGATHER(SDNode *N) {
1255912558
SDValue DAGCombiner::visitMLOAD(SDNode *N) {
1256012559
MaskedLoadSDNode *MLD = cast<MaskedLoadSDNode>(N);
1256112560
SDValue Mask = MLD->getMask();
12562-
SDLoc DL(N);
1256312561

1256412562
// Zap masked loads with a zero mask.
1256512563
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode()))
@@ -23725,7 +23723,6 @@ SDValue DAGCombiner::reduceBuildVecTruncToBitCast(SDNode *N) {
2372523723
if (!DAG.getDataLayout().isLittleEndian())
2372623724
return SDValue();
2372723725

23728-
SDLoc DL(N);
2372923726
EVT OutScalarTy = VT.getScalarType();
2373023727
uint64_t ScalarTypeBitsize = OutScalarTy.getSizeInBits();
2373123728

‎llvm/lib/LTO/LTO.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -634,7 +634,6 @@ void LTO::addModuleToGlobalRes(ArrayRef<InputFile::Symbol> Syms,
634634
auto *ResI = Res.begin();
635635
auto *ResE = Res.end();
636636
(void)ResE;
637-
const Triple TT(RegularLTO.CombinedModule->getTargetTriple());
638637
for (const InputFile::Symbol &Sym : Syms) {
639638
assert(ResI != ResE);
640639
SymbolResolution Res = *ResI++;

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3099,7 +3099,6 @@ AArch64TargetLowering::EmitDynamicProbedAlloc(MachineInstr &MI,
30993099
MachineBasicBlock *MBB) const {
31003100
MachineFunction &MF = *MBB->getParent();
31013101
MachineBasicBlock::iterator MBBI = MI.getIterator();
3102-
DebugLoc DL = MBB->findDebugLoc(MBBI);
31033102
const AArch64InstrInfo &TII =
31043103
*MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
31053104
Register TargetReg = MI.getOperand(0).getReg();
@@ -11953,7 +11952,6 @@ SDValue AArch64TargetLowering::LowerSPONENTRY(SDValue Op,
1195311952
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1195411953

1195511954
EVT VT = getPointerTy(DAG.getDataLayout());
11956-
SDLoc DL(Op);
1195711955
int FI = MFI.CreateFixedObject(4, 0, false);
1195811956
return DAG.getFrameIndex(FI, VT);
1195911957
}

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -997,7 +997,6 @@ void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
997997
}
998998

999999
void AMDGPUDAGToDAGISel::SelectAddcSubb(SDNode *N) {
1000-
SDLoc DL(N);
10011000
SDValue LHS = N->getOperand(0);
10021001
SDValue RHS = N->getOperand(1);
10031002
SDValue CI = N->getOperand(2);
@@ -1050,7 +1049,6 @@ void AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) {
10501049
}
10511050

10521051
void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
1053-
SDLoc SL(N);
10541052
// src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp, omod
10551053
SDValue Ops[10];
10561054

@@ -1071,7 +1069,6 @@ void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
10711069
}
10721070

10731071
void AMDGPUDAGToDAGISel::SelectFMUL_W_CHAIN(SDNode *N) {
1074-
SDLoc SL(N);
10751072
// src0_modifiers, src0, src1_modifiers, src1, clamp, omod
10761073
SDValue Ops[8];
10771074

@@ -1086,7 +1083,6 @@ void AMDGPUDAGToDAGISel::SelectFMUL_W_CHAIN(SDNode *N) {
10861083
// We need to handle this here because tablegen doesn't support matching
10871084
// instructions with multiple outputs.
10881085
void AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
1089-
SDLoc SL(N);
10901086
EVT VT = N->getValueType(0);
10911087

10921088
assert(VT == MVT::f32 || VT == MVT::f64);

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2629,8 +2629,6 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
26292629
assert(MRI.getRegBankOrNull(DstReg) == &AMDGPU::VGPRRegBank &&
26302630
"The destination operand should be in vector registers.");
26312631

2632-
DebugLoc DL = MI.getDebugLoc();
2633-
26342632
// Extract the lower subregister from the first operand.
26352633
Register Op0L = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
26362634
MRI.setRegClass(Op0L, &AMDGPU::VGPR_32RegClass);

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11807,7 +11807,6 @@ static unsigned getBasePtrIndex(const MemSDNode *N) {
1180711807
SDValue SITargetLowering::performMemSDNodeCombine(MemSDNode *N,
1180811808
DAGCombinerInfo &DCI) const {
1180911809
SelectionDAG &DAG = DCI.DAG;
11810-
SDLoc SL(N);
1181111810

1181211811
unsigned PtrIdx = getBasePtrIndex(N);
1181311812
SDValue Ptr = N->getOperand(PtrIdx);

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10624,7 +10624,6 @@ SDValue ARMTargetLowering::LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const {
1062410624
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1062510625

1062610626
EVT VT = getPointerTy(DAG.getDataLayout());
10627-
SDLoc DL(Op);
1062810627
int FI = MFI.CreateFixedObject(4, 0, false);
1062910628
return DAG.getFrameIndex(FI, VT);
1063010629
}
@@ -12453,7 +12452,6 @@ static void attachMEMCPYScratchRegs(const ARMSubtarget *Subtarget,
1245312452
MachineInstr &MI, const SDNode *Node) {
1245412453
bool isThumb1 = Subtarget->isThumb1Only();
1245512454

12456-
DebugLoc DL = MI.getDebugLoc();
1245712455
MachineFunction *MF = MI.getParent()->getParent();
1245812456
MachineRegisterInfo &MRI = MF->getRegInfo();
1245912457
MachineInstrBuilder MIB(*MF, MI);

‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11846,7 +11846,6 @@ bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
1184611846
return Error(L, "Unknown arch name");
1184711847

1184811848
bool WasThumb = isThumb();
11849-
Triple T;
1185011849
MCSubtargetInfo &STI = copySTI();
1185111850
STI.setDefaultFeatures("", /*TuneCPU*/ "",
1185211851
("+" + ARM::getArchName(ID)).str());

‎llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -571,7 +571,6 @@ void AVRDAGToDAGISel::Select(SDNode *N) {
571571

572572
bool AVRDAGToDAGISel::trySelect(SDNode *N) {
573573
unsigned Opcode = N->getOpcode();
574-
SDLoc DL(N);
575574

576575
switch (Opcode) {
577576
// Nodes we fully handle.

‎llvm/lib/Target/BPF/BPFMIChecking.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -159,7 +159,6 @@ void BPFMIPreEmitChecking::processAtomicInsts() {
159159

160160
LLVM_DEBUG(MI.dump());
161161
if (hasLiveDefs(MI, TRI)) {
162-
DebugLoc Empty;
163162
const DebugLoc &DL = MI.getDebugLoc();
164163
const Function &F = MF->getFunction();
165164
F.getContext().diagnose(DiagnosticInfoUnsupported{

‎llvm/lib/Target/Hexagon/HexagonVExtract.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,6 @@ bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) {
161161
assert(ExtI->getOperand(1).getReg() == VecR);
162162

163163
MachineBasicBlock &ExtB = *ExtI->getParent();
164-
DebugLoc DL = ExtI->getDebugLoc();
165164
Register BaseR = EmitAddr(ExtB, ExtI, ExtI->getDebugLoc(), FI,
166165
SR == 0 ? 0 : VecSize/2);
167166

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2549,7 +2549,6 @@ static SDValue checkIntrinsicImmArg(SDValue Op, unsigned ImmOp,
25492549
SDValue
25502550
LoongArchTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
25512551
SelectionDAG &DAG) const {
2552-
SDLoc DL(Op);
25532552
switch (Op.getConstantOperandVal(0)) {
25542553
default:
25552554
return SDValue(); // Don't custom lower most intrinsics.

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2709,7 +2709,6 @@ static SDValue LowerTcgen05St(SDValue Op, SelectionDAG &DAG) {
27092709
static SDValue LowerIntrinsicVoid(SDValue Op, SelectionDAG &DAG) {
27102710
SDNode *N = Op.getNode();
27112711
SDValue Intrin = N->getOperand(1);
2712-
SDLoc DL(N);
27132712

27142713
// Get the intrinsic ID
27152714
unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();

‎llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2975,7 +2975,6 @@ SDNode *IntegerCompareEliminator::tryEXTEND(SDNode *N) {
29752975
if (!WideRes)
29762976
return nullptr;
29772977

2978-
SDLoc dl(N);
29792978
bool Input32Bit = WideRes.getValueType() == MVT::i32;
29802979
bool Output32Bit = N->getValueType(0) == MVT::i32;
29812980

‎llvm/lib/Target/Sparc/SparcISelLowering.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2614,7 +2614,6 @@ static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
26142614
static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
26152615
const SparcTargetLowering &TLI,
26162616
bool hasHardQuad) {
2617-
SDLoc dl(Op);
26182617
EVT VT = Op.getValueType();
26192618

26202619
// Expand if it does not involve f128 or the target has support for
@@ -2635,7 +2634,6 @@ static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
26352634
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
26362635
const SparcTargetLowering &TLI,
26372636
bool hasHardQuad) {
2638-
SDLoc dl(Op);
26392637
EVT OpVT = Op.getOperand(0).getValueType();
26402638
assert(OpVT == MVT::i32 || OpVT == MVT::i64);
26412639

@@ -3158,7 +3156,6 @@ static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
31583156
SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
31593157
SelectionDAG &DAG) const {
31603158
unsigned IntNo = Op.getConstantOperandVal(0);
3161-
SDLoc dl(Op);
31623159
switch (IntNo) {
31633160
default: return SDValue(); // Don't custom lower most intrinsics.
31643161
case Intrinsic::thread_pointer: {

‎llvm/lib/Target/VE/VEISelDAGToDAG.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -249,7 +249,6 @@ bool VEDAGToDAGISel::matchADDRri(SDValue Addr, SDValue &Base, SDValue &Offset) {
249249
}
250250

251251
void VEDAGToDAGISel::Select(SDNode *N) {
252-
SDLoc dl(N);
253252
if (N->isMachineOpcode()) {
254253
N->setNodeId(-1);
255254
return; // Already selected.

‎llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2512,7 +2512,6 @@ SDValue X86DAGToDAGISel::matchIndexRecursively(SDValue N,
25122512

25132513
bool X86DAGToDAGISel::matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
25142514
unsigned Depth) {
2515-
SDLoc dl(N);
25162515
LLVM_DEBUG({
25172516
dbgs() << "MatchAddress: ";
25182517
AM.dump(CurDAG);
@@ -2903,7 +2902,6 @@ bool X86DAGToDAGISel::matchAddressBase(SDValue N, X86ISelAddressMode &AM) {
29032902
bool X86DAGToDAGISel::matchVectorAddressRecursively(SDValue N,
29042903
X86ISelAddressMode &AM,
29052904
unsigned Depth) {
2906-
SDLoc dl(N);
29072905
LLVM_DEBUG({
29082906
dbgs() << "MatchVectorAddress: ";
29092907
AM.dump(CurDAG);

‎llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6592,7 +6592,6 @@ struct VarArgPowerPC64Helper : public VarArgHelperBase {
65926592

65936593
// Instrument va_start.
65946594
// Copy va_list shadow from the backup copy of the TLS contents.
6595-
Triple TargetTriple(F.getParent()->getTargetTriple());
65966595
for (CallInst *OrigInst : VAStartInstrumentationList) {
65976596
NextNodeIRBuilder IRB(OrigInst);
65986597
Value *VAListTag = OrigInst->getArgOperand(0);
@@ -6625,7 +6624,6 @@ struct VarArgPowerPC32Helper : public VarArgHelperBase {
66256624

66266625
void visitCallBase(CallBase &CB, IRBuilder<> &IRB) override {
66276626
unsigned VAArgBase;
6628-
Triple TargetTriple(F.getParent()->getTargetTriple());
66296627
// Parameter save area is 8 bytes from frame pointer in PPC32
66306628
VAArgBase = 8;
66316629
unsigned VAArgOffset = VAArgBase;
@@ -6730,7 +6728,6 @@ struct VarArgPowerPC32Helper : public VarArgHelperBase {
67306728

67316729
// Instrument va_start.
67326730
// Copy va_list shadow from the backup copy of the TLS contents.
6733-
Triple TargetTriple(F.getParent()->getTargetTriple());
67346731
for (CallInst *OrigInst : VAStartInstrumentationList) {
67356732
NextNodeIRBuilder IRB(OrigInst);
67366733
Value *VAListTag = OrigInst->getArgOperand(0);

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