@@ -22,15 +22,7 @@ define i32 @test1(i32 %i) {
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define <2 x i32 > @test1_vector (<2 x i32 > %i ) {
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; CHECK-LABEL: @test1_vector(
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- ; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i32> [[I:%.*]], <i32 24, i32 24>
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- ; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i32> [[I]], <i32 8, i32 8>
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- ; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T3]], <i32 65280, i32 65280>
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- ; CHECK-NEXT: [[T5:%.*]] = or <2 x i32> [[T1]], [[T4]]
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- ; CHECK-NEXT: [[T7:%.*]] = shl <2 x i32> [[I]], <i32 8, i32 8>
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- ; CHECK-NEXT: [[T8:%.*]] = and <2 x i32> [[T7]], <i32 16711680, i32 16711680>
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- ; CHECK-NEXT: [[T9:%.*]] = or <2 x i32> [[T5]], [[T8]]
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- ; CHECK-NEXT: [[T11:%.*]] = shl <2 x i32> [[I]], <i32 24, i32 24>
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- ; CHECK-NEXT: [[T12:%.*]] = or <2 x i32> [[T9]], [[T11]]
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+ ; CHECK-NEXT: [[T12:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[I:%.*]])
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; CHECK-NEXT: ret <2 x i32> [[T12]]
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;
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%t1 = lshr <2 x i32 > %i , <i32 24 , i32 24 >
@@ -64,15 +56,7 @@ define i32 @test2(i32 %arg) {
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define <2 x i32 > @test2_vector (<2 x i32 > %arg ) {
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; CHECK-LABEL: @test2_vector(
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- ; CHECK-NEXT: [[T2:%.*]] = shl <2 x i32> [[ARG:%.*]], <i32 24, i32 24>
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- ; CHECK-NEXT: [[T4:%.*]] = shl <2 x i32> [[ARG]], <i32 8, i32 8>
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- ; CHECK-NEXT: [[T5:%.*]] = and <2 x i32> [[T4]], <i32 16711680, i32 16711680>
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- ; CHECK-NEXT: [[T6:%.*]] = or <2 x i32> [[T2]], [[T5]]
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- ; CHECK-NEXT: [[T8:%.*]] = lshr <2 x i32> [[ARG]], <i32 8, i32 8>
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- ; CHECK-NEXT: [[T9:%.*]] = and <2 x i32> [[T8]], <i32 65280, i32 65280>
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- ; CHECK-NEXT: [[T10:%.*]] = or <2 x i32> [[T6]], [[T9]]
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- ; CHECK-NEXT: [[T12:%.*]] = lshr <2 x i32> [[ARG]], <i32 24, i32 24>
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- ; CHECK-NEXT: [[T14:%.*]] = or <2 x i32> [[T10]], [[T12]]
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+ ; CHECK-NEXT: [[T14:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[ARG:%.*]])
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; CHECK-NEXT: ret <2 x i32> [[T14]]
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;
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%t2 = shl <2 x i32 > %arg , <i32 24 , i32 24 >
@@ -225,15 +209,7 @@ define i32 @test6(i32 %x) nounwind readnone {
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define <2 x i32 > @test6_vector (<2 x i32 > %x ) nounwind readnone {
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; CHECK-LABEL: @test6_vector(
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- ; CHECK-NEXT: [[T:%.*]] = shl <2 x i32> [[X:%.*]], <i32 16, i32 16>
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- ; CHECK-NEXT: [[X_MASK:%.*]] = and <2 x i32> [[X]], <i32 65280, i32 65280>
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- ; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i32> [[X]], <i32 16, i32 16>
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- ; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[T1]], <i32 255, i32 255>
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- ; CHECK-NEXT: [[T3:%.*]] = or <2 x i32> [[X_MASK]], [[T]]
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- ; CHECK-NEXT: [[T4:%.*]] = or <2 x i32> [[T3]], [[T2]]
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- ; CHECK-NEXT: [[T5:%.*]] = shl <2 x i32> [[T4]], <i32 8, i32 8>
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- ; CHECK-NEXT: [[T6:%.*]] = lshr <2 x i32> [[X]], <i32 24, i32 24>
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- ; CHECK-NEXT: [[T7:%.*]] = or <2 x i32> [[T5]], [[T6]]
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+ ; CHECK-NEXT: [[T7:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[X:%.*]])
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; CHECK-NEXT: ret <2 x i32> [[T7]]
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;
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%t = shl <2 x i32 > %x , <i32 16 , i32 16 >
@@ -381,12 +357,9 @@ define i16 @test10(i32 %a) {
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define <2 x i16 > @test10_vector (<2 x i32 > %a ) {
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; CHECK-LABEL: @test10_vector(
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- ; CHECK-NEXT: [[SHR1:%.*]] = lshr <2 x i32> [[A:%.*]], <i32 8, i32 8>
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- ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[SHR1]], <i32 255, i32 255>
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- ; CHECK-NEXT: [[AND2:%.*]] = shl <2 x i32> [[A]], <i32 8, i32 8>
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- ; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[AND1]], [[AND2]]
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- ; CHECK-NEXT: [[CONV:%.*]] = trunc <2 x i32> [[OR]] to <2 x i16>
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- ; CHECK-NEXT: ret <2 x i16> [[CONV]]
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+ ; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i32> [[A:%.*]] to <2 x i16>
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+ ; CHECK-NEXT: [[REV:%.*]] = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> [[TRUNC]])
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+ ; CHECK-NEXT: ret <2 x i16> [[REV]]
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;
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%shr1 = lshr <2 x i32 > %a , <i32 8 , i32 8 >
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%and1 = and <2 x i32 > %shr1 , <i32 255 , i32 255 >
@@ -457,12 +430,10 @@ define i64 @PR39793_bswap_u64_as_u16(i64 %0) {
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define <2 x i64 > @PR39793_bswap_u64_as_u16_vector (<2 x i64 > %0 ) {
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; CHECK-LABEL: @PR39793_bswap_u64_as_u16_vector(
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- ; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i64> [[TMP0:%.*]], <i64 8, i64 8>
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- ; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i64> [[TMP2]], <i64 255, i64 255>
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- ; CHECK-NEXT: [[TMP4:%.*]] = shl <2 x i64> [[TMP0]], <i64 8, i64 8>
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- ; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP4]], <i64 65280, i64 65280>
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- ; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP3]], [[TMP5]]
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- ; CHECK-NEXT: ret <2 x i64> [[TMP6]]
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+ ; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> [[TMP0:%.*]] to <2 x i16>
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+ ; CHECK-NEXT: [[REV:%.*]] = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> [[TRUNC]])
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+ ; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i16> [[REV]] to <2 x i64>
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+ ; CHECK-NEXT: ret <2 x i64> [[TMP2]]
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;
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%2 = lshr <2 x i64 > %0 , <i64 8 , i64 8 >
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%3 = and <2 x i64 > %2 , <i64 255 , i64 255 >
@@ -550,14 +521,8 @@ declare i32 @llvm.bswap.i32(i32)
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define <2 x i32 > @partial_bswap_vector (<2 x i32 > %x ) {
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; CHECK-LABEL: @partial_bswap_vector(
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- ; CHECK-NEXT: [[X3:%.*]] = shl <2 x i32> [[X:%.*]], <i32 24, i32 24>
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- ; CHECK-NEXT: [[A2:%.*]] = shl <2 x i32> [[X]], <i32 8, i32 8>
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- ; CHECK-NEXT: [[X2:%.*]] = and <2 x i32> [[A2]], <i32 16711680, i32 16711680>
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- ; CHECK-NEXT: [[X32:%.*]] = or <2 x i32> [[X3]], [[X2]]
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- ; CHECK-NEXT: [[T1:%.*]] = and <2 x i32> [[X]], <i32 -65536, i32 -65536>
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- ; CHECK-NEXT: [[T2:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[T1]])
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- ; CHECK-NEXT: [[R:%.*]] = or <2 x i32> [[X32]], [[T2]]
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- ; CHECK-NEXT: ret <2 x i32> [[R]]
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+ ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[X:%.*]])
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+ ; CHECK-NEXT: ret <2 x i32> [[TMP1]]
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;
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%x3 = shl <2 x i32 > %x , <i32 24 , i32 24 >
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%a2 = shl <2 x i32 > %x , <i32 8 , i32 8 >
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