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[LoongArch] Pre-commit test for vreplgr2vr + vinsgr2vr intrinsics (#115702)
Inspired by #101624. A later commit will optimize it.
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‎llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl-ins-gr2vr.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define <8 x i32> @xvrepl_ins_w(i32 %a, i32 %b) {
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; CHECK-LABEL: xvrepl_ins_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 0
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; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 1
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; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 2
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; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 3
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; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 4
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; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 5
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; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 6
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; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 7
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; CHECK-NEXT: ret
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entry:
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%0 = call <8 x i32> @llvm.loongarch.lasx.xvreplgr2vr.w(i32 %a)
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%1 = call <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32> %0, i32 %b, i32 1)
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ret <8 x i32> %1
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}
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define <4 x i64> @xvrepl_ins_d(i64 %a, i64 %b) {
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; CHECK-LABEL: xvrepl_ins_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 0
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; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 1
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; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 2
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; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 3
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; CHECK-NEXT: ret
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entry:
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%0 = call <4 x i64> @llvm.loongarch.lasx.xvreplgr2vr.d(i64 %a)
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%1 = call <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64> %0, i64 %b, i32 1)
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ret <4 x i64> %1
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}
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declare <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32>, i32, i32 immarg)
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declare <8 x i32> @llvm.loongarch.lasx.xvreplgr2vr.w(i32)
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declare <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64>, i64, i32 immarg)
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declare <4 x i64> @llvm.loongarch.lasx.xvreplgr2vr.d(i64)

‎llvm/test/CodeGen/LoongArch/lsx/intrinsic-repl-ins-gr2vr.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define <16 x i8> @vrepl_ins_b(i32 %a, i32 %b) {
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; CHECK-LABEL: vrepl_ins_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 1
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 2
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 3
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 4
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 5
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 6
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 7
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 8
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 9
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 10
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 11
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 12
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 13
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 14
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; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 15
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; CHECK-NEXT: ret
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entry:
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%0 = call <16 x i8> @llvm.loongarch.lsx.vreplgr2vr.b(i32 %a)
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%1 = call <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8> %0, i32 %b, i32 1)
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ret <16 x i8> %1
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}
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define <8 x i16> @vrepl_ins_h(i32 %a, i32 %b) {
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; CHECK-LABEL: vrepl_ins_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 1
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 2
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 3
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 4
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 5
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 6
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 7
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; CHECK-NEXT: ret
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entry:
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%0 = call <8 x i16> @llvm.loongarch.lsx.vreplgr2vr.h(i32 %a)
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%1 = call <8 x i16> @llvm.loongarch.lsx.vinsgr2vr.h(<8 x i16> %0, i32 %b, i32 1)
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ret <8 x i16> %1
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}
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define <4 x i32> @vrepl_ins_w(i32 %a, i32 %b) {
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; CHECK-LABEL: vrepl_ins_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 1
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 2
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
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; CHECK-NEXT: ret
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entry:
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%0 = call <4 x i32> @llvm.loongarch.lsx.vreplgr2vr.w(i32 %a)
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%1 = call <4 x i32> @llvm.loongarch.lsx.vinsgr2vr.w(<4 x i32> %0, i32 %b, i32 1)
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ret <4 x i32> %1
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}
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define <2 x i64> @vrepl_ins_d(i64 %a, i64 %b) {
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; CHECK-LABEL: vrepl_ins_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 1
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; CHECK-NEXT: ret
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entry:
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%0 = call <2 x i64> @llvm.loongarch.lsx.vreplgr2vr.d(i64 %a)
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%1 = call <2 x i64> @llvm.loongarch.lsx.vinsgr2vr.d(<2 x i64> %0, i64 %b, i32 1)
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ret <2 x i64> %1
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}
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declare <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8>, i32, i32 immarg)
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declare <16 x i8> @llvm.loongarch.lsx.vreplgr2vr.b(i32)
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declare <8 x i16> @llvm.loongarch.lsx.vinsgr2vr.h(<8 x i16>, i32, i32 immarg)
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declare <8 x i16> @llvm.loongarch.lsx.vreplgr2vr.h(i32)
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declare <4 x i32> @llvm.loongarch.lsx.vinsgr2vr.w(<4 x i32>, i32, i32 immarg)
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declare <4 x i32> @llvm.loongarch.lsx.vreplgr2vr.w(i32)
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declare <2 x i64> @llvm.loongarch.lsx.vinsgr2vr.d(<2 x i64>, i64, i32 immarg)
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declare <2 x i64> @llvm.loongarch.lsx.vreplgr2vr.d(i64)

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