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SahilPatidarSahilPatidar
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[DAG] computeKnownBits - add ISD::ABDU/ISD::ABDS handling #84905 (#88253)
Resolve #84905
1 parent 5ebeaf2 commit ab037c4

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3 files changed

+174
-7
lines changed

3 files changed

+174
-7
lines changed

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3397,6 +3397,18 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
33973397
Known = KnownBits::mulhs(Known, Known2);
33983398
break;
33993399
}
3400+
case ISD::ABDU: {
3401+
Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3402+
Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3403+
Known = KnownBits::abdu(Known, Known2);
3404+
break;
3405+
}
3406+
case ISD::ABDS: {
3407+
Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3408+
Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
3409+
Known = KnownBits::abds(Known, Known2);
3410+
break;
3411+
}
34003412
case ISD::UMUL_LOHI: {
34013413
assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result");
34023414
Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);

‎llvm/test/CodeGen/AArch64/abd-combine.ll

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -530,13 +530,11 @@ define <8 x i16> @abds_i_reassoc(<8 x i16> %src1) {
530530
define <1 x i64> @recursive() {
531531
; CHECK-LABEL: recursive:
532532
; CHECK: // %bb.0:
533-
; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff
534-
; CHECK-NEXT: movi v1.8b, #1
535-
; CHECK-NEXT: uabd v2.8b, v1.8b, v0.8b
536-
; CHECK-NEXT: uabdl v0.8h, v1.8b, v0.8b
537-
; CHECK-NEXT: dup v1.8b, v2.b[0]
538-
; CHECK-NEXT: saddlp v0.1d, v0.2s
539-
; CHECK-NEXT: orr v0.8b, v1.8b, v0.8b
533+
; CHECK-NEXT: movi v0.8b, #254
534+
; CHECK-NEXT: ushll v1.8h, v0.8b, #0
535+
; CHECK-NEXT: dup v0.8b, v0.b[0]
536+
; CHECK-NEXT: saddlp v1.1d, v1.2s
537+
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
540538
; CHECK-NEXT: ret
541539
%1 = tail call <8 x i8> @llvm.aarch64.neon.umax.v8i8(<8 x i8> zeroinitializer, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
542540
%2 = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)

‎llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll

Lines changed: 157 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -291,3 +291,160 @@ define <2 x double> @test_fabd_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
291291
%abd = call <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double> %lhs, <2 x double> %rhs)
292292
ret <2 x double> %abd
293293
}
294+
295+
define <8 x i16> @test_uabd_knownbits_vec8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
296+
; CHECK-LABEL: test_uabd_knownbits_vec8i16:
297+
; CHECK: // %bb.0:
298+
; CHECK-NEXT: movi v2.8h, #15
299+
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
300+
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
301+
; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h
302+
; CHECK-NEXT: rev64 v0.8h, v0.8h
303+
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
304+
; CHECK-NEXT: ret
305+
%and1 = and <8 x i16> %lhs, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
306+
%and2 = and <8 x i16> %rhs, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
307+
%uabd = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %and1, <8 x i16> %and2)
308+
%suff = shufflevector <8 x i16> %uabd, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
309+
%res = and <8 x i16> %suff, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
310+
ret <8 x i16> %res
311+
}
312+
313+
define <4 x i32> @knownbits_uabd_mask_and_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) {
314+
; CHECK-LABEL: knownbits_uabd_mask_and_shuffle_lshr:
315+
; CHECK: // %bb.0:
316+
; CHECK-NEXT: movi v0.2d, #0000000000000000
317+
; CHECK-NEXT: ushr v0.4s, v0.4s, #17
318+
; CHECK-NEXT: ret
319+
%1 = and <4 x i32> %a0, <i32 65535, i32 65535, i32 65535, i32 65535>
320+
%2 = and <4 x i32> %a1, <i32 65535, i32 65535, i32 65535, i32 65535>
321+
%3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %1, <4 x i32> %2)
322+
%4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
323+
%5 = lshr <4 x i32> %4, <i32 17, i32 17, i32 17, i32 17>
324+
ret <4 x i32> %5
325+
}
326+
327+
define <4 x i32> @knownbits_mask_and_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) {
328+
; CHECK-LABEL: knownbits_mask_and_shuffle_lshr:
329+
; CHECK: // %bb.0:
330+
; CHECK-NEXT: movi v0.2d, #0000000000000000
331+
; CHECK-NEXT: ret
332+
%1 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
333+
%2 = and <4 x i32> %a1, <i32 32767, i32 32767, i32 32767, i32 32767>
334+
%3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %1, <4 x i32> %2)
335+
%4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
336+
%5 = lshr <4 x i32> %4, <i32 17, i32 17, i32 17, i32 17>
337+
ret <4 x i32> %5
338+
}
339+
340+
define <4 x i32> @test_sabd_knownbits_vec4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
341+
; CHECK-LABEL: test_sabd_knownbits_vec4i32:
342+
; CHECK: // %bb.0:
343+
; CHECK-NEXT: adrp x8, .LCPI31_0
344+
; CHECK-NEXT: adrp x9, .LCPI31_1
345+
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI31_0]
346+
; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI31_1]
347+
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
348+
; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
349+
; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
350+
; CHECK-NEXT: movi v1.2d, #0x0000ff000000ff
351+
; CHECK-NEXT: mov v0.s[1], v0.s[0]
352+
; CHECK-NEXT: trn2 v0.4s, v0.4s, v0.4s
353+
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
354+
; CHECK-NEXT: ret
355+
%and1 = and <4 x i32> %lhs, <i32 255, i32 -1, i32 -1, i32 255>
356+
%and2 = and <4 x i32> %rhs, <i32 255, i32 255, i32 -1, i32 -1>
357+
%abd = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %and1, <4 x i32> %and2)
358+
%s = shufflevector <4 x i32> %abd, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>
359+
%4 = and <4 x i32> %s, <i32 255, i32 255, i32 255, i32 255>
360+
ret <4 x i32> %4
361+
}
362+
363+
define <4 x i32> @knownbits_sabd_and_mask(<4 x i32> %a0, <4 x i32> %a1) {
364+
; CHECK-LABEL: knownbits_sabd_and_mask:
365+
; CHECK: // %bb.0:
366+
; CHECK-NEXT: adrp x8, .LCPI32_0
367+
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI32_0]
368+
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
369+
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
370+
; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
371+
; CHECK-NEXT: zip2 v0.4s, v0.4s, v0.4s
372+
; CHECK-NEXT: ret
373+
%1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
374+
%2 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 255, i32 4085>
375+
%3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %1, <4 x i32> %2)
376+
%4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
377+
ret <4 x i32> %4
378+
}
379+
380+
define <4 x i32> @knownbits_sabd_and_or_mask(<4 x i32> %a0, <4 x i32> %a1) {
381+
; CHECK-LABEL: knownbits_sabd_and_or_mask:
382+
; CHECK: // %bb.0:
383+
; CHECK-NEXT: movi v0.2d, #0000000000000000
384+
; CHECK-NEXT: ret
385+
%1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
386+
%2 = or <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535>
387+
%3 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 255, i32 4085>
388+
%4 = or <4 x i32> %3, <i32 65535, i32 65535, i32 65535, i32 65535>
389+
%5 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %2, <4 x i32> %4)
390+
%6 = shufflevector <4 x i32> %5, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
391+
ret <4 x i32> %6
392+
}
393+
394+
define <4 x i32> @knownbits_sabd_and_xor_mask(<4 x i32> %a0, <4 x i32> %a1) {
395+
; CHECK-LABEL: knownbits_sabd_and_xor_mask:
396+
; CHECK: // %bb.0:
397+
; CHECK-NEXT: adrp x8, .LCPI34_0
398+
; CHECK-NEXT: movi v3.2d, #0x00ffff0000ffff
399+
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI34_0]
400+
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
401+
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
402+
; CHECK-NEXT: eor v0.16b, v0.16b, v3.16b
403+
; CHECK-NEXT: eor v1.16b, v1.16b, v3.16b
404+
; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
405+
; CHECK-NEXT: zip2 v0.4s, v0.4s, v0.4s
406+
; CHECK-NEXT: ret
407+
%1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
408+
%2 = xor <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535>
409+
%3 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 255, i32 4085>
410+
%4 = xor <4 x i32> %3, <i32 65535, i32 65535, i32 65535, i32 65535>
411+
%5 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %2, <4 x i32> %4)
412+
%6 = shufflevector <4 x i32> %5, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
413+
ret <4 x i32> %6
414+
}
415+
416+
define <4 x i32> @knownbits_sabd_and_shl_mask(<4 x i32> %a0, <4 x i32> %a1) {
417+
; CHECK-LABEL: knownbits_sabd_and_shl_mask:
418+
; CHECK: // %bb.0:
419+
; CHECK-NEXT: movi v0.2d, #0000000000000000
420+
; CHECK-NEXT: ret
421+
%1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536>
422+
%2 = shl <4 x i32> %1, <i32 17, i32 17, i32 17, i32 17>
423+
%3 = and <4 x i32> %a1, <i32 -65536, i32 -7, i32 -7, i32 -65536>
424+
%4 = shl <4 x i32> %3, <i32 17, i32 17, i32 17, i32 17>
425+
%5 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %2, <4 x i32> %4)
426+
%6 = shufflevector <4 x i32> %5, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>
427+
ret <4 x i32> %6
428+
}
429+
430+
define <4 x i32> @knownbits_sabd_and_mul_mask(<4 x i32> %a0, <4 x i32> %a1) {
431+
; CHECK-LABEL: knownbits_sabd_and_mul_mask:
432+
; CHECK: // %bb.0:
433+
; CHECK-NEXT: adrp x8, .LCPI36_0
434+
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI36_0]
435+
; CHECK-NEXT: and v3.16b, v0.16b, v2.16b
436+
; CHECK-NEXT: and v2.16b, v1.16b, v2.16b
437+
; CHECK-NEXT: mul v0.4s, v0.4s, v3.4s
438+
; CHECK-NEXT: mul v1.4s, v1.4s, v2.4s
439+
; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
440+
; CHECK-NEXT: mov v0.s[1], v0.s[0]
441+
; CHECK-NEXT: trn2 v0.4s, v0.4s, v0.4s
442+
; CHECK-NEXT: ret
443+
%1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536>
444+
%2 = mul <4 x i32> %a0, %1
445+
%3 = and <4 x i32> %a1, <i32 -65536, i32 -7, i32 -7, i32 -65536>
446+
%4 = mul <4 x i32> %a1, %3
447+
%5 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %2, <4 x i32> %4)
448+
%6 = shufflevector <4 x i32> %5, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>
449+
ret <4 x i32> %6
450+
}

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