Addressed changes in comments.

Author: vg0204

llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir

@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -stress-regalloc=3 -start-before=greedy,0 -stop-after=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR_SPILLED %s
 
-# INFO : The pass pipeline is started from before the first iteration of register allocation pass that represents SGPR allocation in AMDGPU pipleine.
+# INFO : The test starts from the sgpr-regalloc pipeline.
 
 # This file contains 3 test cases to observe the optimal stack slot usage for SGPR spills utilizing Stack Slot Coloring pass.
 # @stack-slot-share-equal-sized-spills : In this, the stack slot indices is shared among the spill stack objects of equal size.
@@ -10,7 +10,6 @@
 # In the remaining 2 test cases mentioned in just above 2 lines, the stack slot indices is shared among the spill stack objects of
 # unequal size, with spill slot having the size of the largest of the stack objects sharing the common stack indices.
 
-
 ---
 name:            stack-slot-share-equal-sized-spills
 tracksRegLiveness: true