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[FMV] Add alias for FEAT_RDM and change priorities according to ACLE.
This patch follows the latest ACLE specification as shown in PR ARM-software/acle#279. It adds a name alias for FEAT_RDM and adjusts priorities for FEAT_DOTPROD, FEAT_SM4, FEAT_FP16FML, FEAT_RDM.
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5 files changed

+42
-27
lines changed

5 files changed

+42
-27
lines changed

‎clang/test/CodeGen/attr-target-version.c

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ inline int __attribute__((target_version("memtag3+rcpc3+mops"))) fmv_inline(void
3939
inline int __attribute__((target_version("aes+dotprod"))) fmv_inline(void) { return 13; }
4040
inline int __attribute__((target_version("simd+fp16fml"))) fmv_inline(void) { return 14; }
4141
inline int __attribute__((target_version("fp+sm4"))) fmv_inline(void) { return 15; }
42-
inline int __attribute__((target_version("lse+rdm"))) fmv_inline(void) { return 16; }
42+
inline int __attribute__((target_version("lse+rdma"))) fmv_inline(void) { return 16; }
4343
inline int __attribute__((target_version("default"))) fmv_inline(void) { return 3; }
4444

4545
__attribute__((target_version("ls64"))) int fmv_e(void);
@@ -364,36 +364,36 @@ int hoo(void) {
364364
// CHECK-NEXT: ret ptr @fmv_inline._Mdpb2Mjscvt
365365
// CHECK: resolver_else22:
366366
// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
367-
// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 16400
368-
// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 16400
367+
// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 8
368+
// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 8
369369
// CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]]
370370
// CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]]
371371
// CHECK: resolver_return23:
372-
// CHECK-NEXT: ret ptr @fmv_inline._MdotprodMaes
372+
// CHECK-NEXT: ret ptr @fmv_inline._MsimdMfp16fml
373373
// CHECK: resolver_else24:
374374
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
375-
// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 8
376-
// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 8
375+
// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 16400
376+
// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 16400
377377
// CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]]
378378
// CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]]
379379
// CHECK: resolver_return25:
380-
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16fmlMsimd
380+
// CHECK-NEXT: ret ptr @fmv_inline._MdotprodMaes
381381
// CHECK: resolver_else26:
382382
// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
383-
// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 32
384-
// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 32
383+
// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 192
384+
// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 192
385385
// CHECK-NEXT: [[TMP59:%.*]] = and i1 true, [[TMP58]]
386386
// CHECK-NEXT: br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]]
387387
// CHECK: resolver_return27:
388-
// CHECK-NEXT: ret ptr @fmv_inline._Msm4Mfp
388+
// CHECK-NEXT: ret ptr @fmv_inline._MlseMrdma
389389
// CHECK: resolver_else28:
390390
// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
391-
// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 192
392-
// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 192
391+
// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 32
392+
// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 32
393393
// CHECK-NEXT: [[TMP63:%.*]] = and i1 true, [[TMP62]]
394394
// CHECK-NEXT: br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]]
395395
// CHECK: resolver_return29:
396-
// CHECK-NEXT: ret ptr @fmv_inline._MrdmMlse
396+
// CHECK-NEXT: ret ptr @fmv_inline._MfpMsm4
397397
// CHECK: resolver_else30:
398398
// CHECK-NEXT: ret ptr @fmv_inline.default
399399
//
@@ -659,21 +659,21 @@ int hoo(void) {
659659
//
660660
//
661661
// CHECK: Function Attrs: noinline nounwind optnone
662-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16fmlMsimd
662+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MsimdMfp16fml
663663
// CHECK-SAME: () #[[ATTR7]] {
664664
// CHECK-NEXT: entry:
665665
// CHECK-NEXT: ret i32 14
666666
//
667667
//
668668
// CHECK: Function Attrs: noinline nounwind optnone
669-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msm4Mfp
669+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfpMsm4
670670
// CHECK-SAME: () #[[ATTR24:[0-9]+]] {
671671
// CHECK-NEXT: entry:
672672
// CHECK-NEXT: ret i32 15
673673
//
674674
//
675675
// CHECK: Function Attrs: noinline nounwind optnone
676-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MrdmMlse
676+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MlseMrdma
677677
// CHECK-SAME: () #[[ATTR25:[0-9]+]] {
678678
// CHECK-NEXT: entry:
679679
// CHECK-NEXT: ret i32 16

‎clang/test/Sema/attr-target-clones-aarch64.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// RUN: %clang_cc1 -triple aarch64-linux-gnu -fsyntax-only -verify %s
22

3-
void __attribute__((target_clones("fp16+sve2-aes", "sb+sve2-sha3+rcpc3+mops"))) no_def(void);
3+
void __attribute__((target_clones("fp16+sve2-aes", "sb+sve2-sha3+rcpc3+mops", "rdma"))) no_def(void);
44

55
// expected-warning@+1 {{unsupported 'default' in the 'target_clones' attribute string; 'target_clones' attribute ignored}}
66
void __attribute__((target_clones("default+sha3"))) warn1(void);

‎clang/test/SemaCXX/attr-target-version.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@ void __attribute__((target_version("dotprod"))) no_def(void);
77
void __attribute__((target_version("rdm+fp"))) no_def(void);
88
void __attribute__((target_version("rcpc3"))) no_def(void);
99
void __attribute__((target_version("mops"))) no_def(void);
10+
void __attribute__((target_version("rdma"))) no_def(void);
1011

1112
// expected-error@+1 {{no matching function for call to 'no_def'}}
1213
void foo(void) { no_def(); }

‎llvm/include/llvm/TargetParser/AArch64TargetParser.h

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ inline constexpr ExtensionInfo Extensions[] = {
222222
{"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0},
223223
{"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260},
224224
{"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180},
225-
{"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD, "+dotprod,+fp-armv8,+neon", 50},
225+
{"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD, "+dotprod,+fp-armv8,+neon", 104},
226226
{"dpb", AArch64::AEK_NONE, {}, {}, FEAT_DPB, "+ccpp", 190},
227227
{"dpb2", AArch64::AEK_NONE, {}, {}, FEAT_DPB2, "+ccpp,+ccdp", 200},
228228
{"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290},
@@ -233,7 +233,7 @@ inline constexpr ExtensionInfo Extensions[] = {
233233
{"flagm2", AArch64::AEK_NONE, {}, {}, FEAT_FLAGM2, "+flagm,+altnzcv", 30},
234234
{"fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8", FEAT_FP, "+fp-armv8,+neon", 90},
235235
{"fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16", FEAT_FP16, "+fullfp16,+fp-armv8,+neon", 170},
236-
{"fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml", FEAT_FP16FML, "+fp16fml,+fullfp16,+fp-armv8,+neon", 40},
236+
{"fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml", FEAT_FP16FML, "+fp16fml,+fullfp16,+fp-armv8,+neon", 175},
237237
{"frintts", AArch64::AEK_NONE, {}, {}, FEAT_FRINTTS, "+fptoint", 250},
238238
{"hbc", AArch64::AEK_HBC, "+hbc", "-hbc", FEAT_INIT, "", 0},
239239
{"i8mm", AArch64::AEK_I8MM, "+i8mm", "-i8mm", FEAT_I8MM, "+i8mm", 270},
@@ -259,15 +259,15 @@ inline constexpr ExtensionInfo Extensions[] = {
259259
{"rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc", FEAT_RCPC, "+rcpc", 230},
260260
{"rcpc2", AArch64::AEK_NONE, {}, {}, FEAT_RCPC2, "+rcpc", 240},
261261
{"rcpc3", AArch64::AEK_RCPC3, "+rcpc3", "-rcpc3", FEAT_RCPC3, "+rcpc,+rcpc3", 241},
262-
{"rdm", AArch64::AEK_RDM, "+rdm", "-rdm", FEAT_RDM, "+rdm,+fp-armv8,+neon", 70},
262+
{"rdm", AArch64::AEK_RDM, "+rdm", "-rdm", FEAT_RDM, "+rdm,+fp-armv8,+neon", 108},
263263
{"rng", AArch64::AEK_RAND, "+rand", "-rand", FEAT_RNG, "+rand", 10},
264264
{"rpres", AArch64::AEK_NONE, {}, {}, FEAT_RPRES, "", 300},
265265
{"sb", AArch64::AEK_SB, "+sb", "-sb", FEAT_SB, "+sb", 470},
266266
{"sha1", AArch64::AEK_NONE, {}, {}, FEAT_SHA1, "+fp-armv8,+neon", 120},
267267
{"sha2", AArch64::AEK_SHA2, "+sha2", "-sha2", FEAT_SHA2, "+sha2,+fp-armv8,+neon", 130},
268268
{"sha3", AArch64::AEK_SHA3, "+sha3", "-sha3", FEAT_SHA3, "+sha3,+sha2,+fp-armv8,+neon", 140},
269269
{"simd", AArch64::AEK_SIMD, "+neon", "-neon", FEAT_SIMD, "+fp-armv8,+neon", 100},
270-
{"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4, "+sm4,+fp-armv8,+neon", 60},
270+
{"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4, "+sm4,+fp-armv8,+neon", 106},
271271
{"sme-f16f16", AArch64::AEK_SMEF16F16, "+sme-f16f16", "-sme-f16f16", FEAT_INIT, "", 0},
272272
{"sme-f64f64", AArch64::AEK_SMEF64F64, "+sme-f64f64", "-sme-f64f64", FEAT_SME_F64, "+sme,+sme-f64f64,+bf16", 560},
273273
{"sme-i16i64", AArch64::AEK_SMEI16I64, "+sme-i16i64", "-sme-i16i64", FEAT_SME_I64, "+sme,+sme-i16i64,+bf16", 570},
@@ -807,20 +807,23 @@ inline constexpr CpuInfo CpuInfos[] = {
807807
AArch64::AEK_MTE, AArch64::AEK_SB, AArch64::AEK_SSBS}))},
808808
};
809809

810-
// An alias for a CPU.
811-
struct CpuAlias {
812-
StringRef Alias;
810+
// Name alias
811+
struct Alias {
812+
StringRef AltName;
813813
StringRef Name;
814814
};
815815

816-
inline constexpr CpuAlias CpuAliases[] = {{"grace", "neoverse-v2"}};
816+
inline constexpr Alias CpuAliases[] = {{"grace", "neoverse-v2"}};
817+
818+
inline constexpr Alias ExtAliases[] = {{"rdma", "rdm"}};
817819

818820
bool getExtensionFeatures(
819821
const AArch64::ExtensionBitset &Extensions,
820822
std::vector<StringRef> &Features);
821823

822824
StringRef getArchExtFeature(StringRef ArchExt);
823825
StringRef resolveCPUAlias(StringRef CPU);
826+
StringRef resolveExtAlias(StringRef ArchExt);
824827

825828
// Information by Name
826829
const ArchInfo *getArchForCpu(StringRef CPU);

‎llvm/lib/TargetParser/AArch64TargetParser.cpp

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,14 @@ bool AArch64::getExtensionFeatures(
6969

7070
StringRef AArch64::resolveCPUAlias(StringRef Name) {
7171
for (const auto &A : CpuAliases)
72-
if (A.Alias == Name)
72+
if (A.AltName == Name)
73+
return A.Name;
74+
return Name;
75+
}
76+
77+
StringRef AArch64::resolveExtAlias(StringRef Name) {
78+
for (const auto &A : ExtAliases)
79+
if (A.AltName == Name)
7380
return A.Name;
7481
return Name;
7582
}
@@ -91,7 +98,7 @@ void AArch64::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
9198
Values.push_back(C.Name);
9299

93100
for (const auto &Alias : CpuAliases)
94-
Values.push_back(Alias.Alias);
101+
Values.push_back(Alias.AltName);
95102
}
96103

97104
bool AArch64::isX18ReservedByDefault(const Triple &TT) {
@@ -114,6 +121,10 @@ const AArch64::ArchInfo *AArch64::parseArch(StringRef Arch) {
114121
}
115122

116123
std::optional<AArch64::ExtensionInfo> AArch64::parseArchExtension(StringRef ArchExt) {
124+
// Resolve aliases first.
125+
ArchExt = resolveExtAlias(ArchExt);
126+
127+
// Then find the Extension name.
117128
for (const auto &A : Extensions) {
118129
if (ArchExt == A.Name)
119130
return A;

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