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[RISCV] Add casts to isel patterns that produce more than 1 instruction.
We need explicitly cast to XLenVT to avoid tablegen picking i32. If the SelectionDAG scheduler is used it can't find a register class for i32 if i32 isn't a legal type. Fixes #81192, but I might have missed some patterns.
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7 files changed

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‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1260,14 +1260,14 @@ def : PatGprSimm12<or_is_add, ADDI>;
12601260
// negate of low bit can be done via two (compressible) shifts. The negate
12611261
// is never compressible since rs1 and rd can't be the same register.
12621262
def : Pat<(XLenVT (sub 0, (and_oneuse GPR:$rs, 1))),
1263-
(SRAI (SLLI $rs, (ImmSubFromXLen (XLenVT 1))),
1263+
(SRAI (XLenVT (SLLI $rs, (ImmSubFromXLen (XLenVT 1)))),
12641264
(ImmSubFromXLen (XLenVT 1)))>;
12651265

12661266
// AND with leading/trailing ones mask exceeding simm32/simm12.
12671267
def : Pat<(i64 (and GPR:$rs, LeadingOnesMask:$mask)),
1268-
(SLLI (SRLI $rs, LeadingOnesMask:$mask), LeadingOnesMask:$mask)>;
1268+
(SLLI (i64 (SRLI $rs, LeadingOnesMask:$mask)), LeadingOnesMask:$mask)>;
12691269
def : Pat<(XLenVT (and GPR:$rs, TrailingOnesMask:$mask)),
1270-
(SRLI (SLLI $rs, TrailingOnesMask:$mask), TrailingOnesMask:$mask)>;
1270+
(SRLI (XLenVT (SLLI $rs, TrailingOnesMask:$mask)), TrailingOnesMask:$mask)>;
12711271

12721272
// Match both a plain shift and one where the shift amount is masked (this is
12731273
// typically introduced when the legalizer promotes the shift amount and
@@ -1380,7 +1380,7 @@ defm Select_GPR : SelectCC_GPR_rrirr<GPR, XLenVT>;
13801380
class SelectCompressOpt<CondCode Cond>
13811381
: Pat<(riscv_selectcc_frag:$select (XLenVT GPR:$lhs), simm12_no6:$Constant, Cond,
13821382
(XLenVT GPR:$truev), GPR:$falsev),
1383-
(Select_GPR_Using_CC_GPR (ADDI GPR:$lhs, (NegImm simm12:$Constant)), (XLenVT X0),
1383+
(Select_GPR_Using_CC_GPR (XLenVT (ADDI GPR:$lhs, (NegImm simm12:$Constant))), (XLenVT X0),
13841384
(IntCCtoRISCVCC $select), GPR:$truev, GPR:$falsev)>;
13851385

13861386
def OptForMinSize : Predicate<"MF ? MF->getFunction().hasMinSize() : false">;
@@ -1728,12 +1728,12 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
17281728
/// RV64 patterns
17291729

17301730
let Predicates = [IsRV64, NotHasStdExtZba] in {
1731-
def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (SLLI GPR:$rs1, 32), 32)>;
1731+
def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (i64 (SLLI GPR:$rs1, 32)), 32)>;
17321732

17331733
// If we're shifting a 32-bit zero extended value left by 0-31 bits, use 2
17341734
// shifts instead of 3. This can occur when unsigned is used to index an array.
17351735
def : Pat<(i64 (shl (and GPR:$rs1, 0xffffffff), uimm5:$shamt)),
1736-
(SRLI (SLLI GPR:$rs1, 32), (ImmSubFrom32 uimm5:$shamt))>;
1736+
(SRLI (i64 (SLLI GPR:$rs1, 32)), (ImmSubFrom32 uimm5:$shamt))>;
17371737
}
17381738

17391739
class binop_allhusers<SDPatternOperator operator>
@@ -1768,7 +1768,7 @@ def u32simm12 : ImmLeaf<XLenVT, [{
17681768
let Predicates = [IsRV64] in {
17691769

17701770
def : Pat<(i64 (and GPR:$rs, LeadingOnesWMask:$mask)),
1771-
(SLLI (SRLIW $rs, LeadingOnesWMask:$mask), LeadingOnesWMask:$mask)>;
1771+
(SLLI (i64 (SRLIW $rs, LeadingOnesWMask:$mask)), LeadingOnesWMask:$mask)>;
17721772

17731773
/// sext and zext
17741774

@@ -1864,13 +1864,13 @@ def KCFI_CHECK
18641864

18651865
/// Simple optimization
18661866
def : Pat<(XLenVT (add GPR:$rs1, (AddiPair:$rs2))),
1867-
(ADDI (ADDI GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2)),
1867+
(ADDI (XLenVT (ADDI GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2))),
18681868
(AddiPairImmSmall GPR:$rs2))>;
18691869

18701870
let Predicates = [IsRV64] in {
18711871
// Select W instructions if only the lower 32-bits of the result are used.
18721872
def : Pat<(binop_allwusers<add> GPR:$rs1, (AddiPair:$rs2)),
1873-
(ADDIW (ADDIW GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2)),
1873+
(ADDIW (i64 (ADDIW GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2))),
18741874
(AddiPairImmSmall AddiPair:$rs2))>;
18751875
}
18761876

@@ -1929,20 +1929,20 @@ def : PatGprImm<srl, SRLIW, uimm5, i32>;
19291929
def : PatGprImm<sra, SRAIW, uimm5, i32>;
19301930

19311931
def : Pat<(i32 (and GPR:$rs, TrailingOnesMask:$mask)),
1932-
(SRLI (SLLI $rs, (i64 (XLenSubTrailingOnes $mask))),
1932+
(SRLI (i32 (SLLI $rs, (i64 (XLenSubTrailingOnes $mask)))),
19331933
(i64 (XLenSubTrailingOnes $mask)))>;
19341934

19351935
// Use sext if the sign bit of the input is 0.
19361936
def : Pat<(zext_is_sext GPR:$src), (ADDIW GPR:$src, 0)>;
19371937
}
19381938

19391939
let Predicates = [IsRV64, NotHasStdExtZba] in {
1940-
def : Pat<(zext GPR:$src), (SRLI (SLLI GPR:$src, 32), 32)>;
1940+
def : Pat<(zext GPR:$src), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
19411941

19421942
// If we're shifting a 32-bit zero extended value left by 0-31 bits, use 2
19431943
// shifts instead of 3. This can occur when unsigned is used to index an array.
19441944
def : Pat<(shl (zext GPR:$rs), uimm5:$shamt),
1945-
(SRLI (SLLI GPR:$rs, 32), (ImmSubFrom32 uimm5:$shamt))>;
1945+
(SRLI (i64 (SLLI GPR:$rs, 32)), (ImmSubFrom32 uimm5:$shamt))>;
19461946
}
19471947

19481948
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoD.td

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -410,11 +410,11 @@ foreach Ext = DExts in {
410410
let Predicates = [HasStdExtD] in {
411411
// Match signaling FEQ_D
412412
def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ)),
413-
(AND (FLE_D $rs1, $rs2),
414-
(FLE_D $rs2, $rs1))>;
413+
(AND (XLenVT (FLE_D $rs1, $rs2)),
414+
(XLenVT (FLE_D $rs2, $rs1)))>;
415415
def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ)),
416-
(AND (FLE_D $rs1, $rs2),
417-
(FLE_D $rs2, $rs1))>;
416+
(AND (XLenVT (FLE_D $rs1, $rs2)),
417+
(XLenVT (FLE_D $rs2, $rs1)))>;
418418
// If both operands are the same, use a single FLE.
419419
def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ)),
420420
(FLE_D $rs1, $rs1)>;
@@ -430,11 +430,11 @@ def : PatSetCC<FPR64, any_fsetccs, SETOLE, FLE_D, f64>;
430430
let Predicates = [HasStdExtZdinx, IsRV64] in {
431431
// Match signaling FEQ_D
432432
def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETEQ)),
433-
(AND (FLE_D_INX $rs1, $rs2),
434-
(FLE_D_INX $rs2, $rs1))>;
433+
(AND (XLenVT (FLE_D_INX $rs1, $rs2)),
434+
(XLenVT (FLE_D_INX $rs2, $rs1)))>;
435435
def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETOEQ)),
436-
(AND (FLE_D_INX $rs1, $rs2),
437-
(FLE_D_INX $rs2, $rs1))>;
436+
(AND (XLenVT (FLE_D_INX $rs1, $rs2)),
437+
(XLenVT (FLE_D_INX $rs2, $rs1)))>;
438438
// If both operands are the same, use a single FLE.
439439
def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs1, SETEQ)),
440440
(FLE_D_INX $rs1, $rs1)>;
@@ -450,11 +450,11 @@ def : PatSetCC<FPR64INX, any_fsetccs, SETOLE, FLE_D_INX, f64>;
450450
let Predicates = [HasStdExtZdinx, IsRV32] in {
451451
// Match signaling FEQ_D
452452
def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETEQ)),
453-
(AND (FLE_D_IN32X $rs1, $rs2),
454-
(FLE_D_IN32X $rs2, $rs1))>;
453+
(AND (XLenVT (FLE_D_IN32X $rs1, $rs2)),
454+
(XLenVT (FLE_D_IN32X $rs2, $rs1)))>;
455455
def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETOEQ)),
456-
(AND (FLE_D_IN32X $rs1, $rs2),
457-
(FLE_D_IN32X $rs2, $rs1))>;
456+
(AND (XLenVT (FLE_D_IN32X $rs1, $rs2)),
457+
(XLenVT (FLE_D_IN32X $rs2, $rs1)))>;
458458
// If both operands are the same, use a single FLE.
459459
def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs1, SETEQ)),
460460
(FLE_D_IN32X $rs1, $rs1)>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoF.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -617,11 +617,11 @@ foreach Ext = FExts in {
617617
let Predicates = [HasStdExtF] in {
618618
// Match signaling FEQ_S
619619
def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ)),
620-
(AND (FLE_S $rs1, $rs2),
621-
(FLE_S $rs2, $rs1))>;
620+
(AND (XLenVT (FLE_S $rs1, $rs2)),
621+
(XLenVT (FLE_S $rs2, $rs1)))>;
622622
def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETOEQ)),
623-
(AND (FLE_S $rs1, $rs2),
624-
(FLE_S $rs2, $rs1))>;
623+
(AND (XLenVT (FLE_S $rs1, $rs2)),
624+
(XLenVT (FLE_S $rs2, $rs1)))>;
625625
// If both operands are the same, use a single FLE.
626626
def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ)),
627627
(FLE_S $rs1, $rs1)>;
@@ -632,11 +632,11 @@ def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETOEQ)),
632632
let Predicates = [HasStdExtZfinx] in {
633633
// Match signaling FEQ_S
634634
def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETEQ)),
635-
(AND (FLE_S_INX $rs1, $rs2),
636-
(FLE_S_INX $rs2, $rs1))>;
635+
(AND (XLenVT (FLE_S_INX $rs1, $rs2)),
636+
(XLenVT (FLE_S_INX $rs2, $rs1)))>;
637637
def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETOEQ)),
638-
(AND (FLE_S_INX $rs1, $rs2),
639-
(FLE_S_INX $rs2, $rs1))>;
638+
(AND (XLenVT (FLE_S_INX $rs1, $rs2)),
639+
(XLenVT (FLE_S_INX $rs2, $rs1)))>;
640640
// If both operands are the same, use a single FLE.
641641
def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs1, SETEQ)),
642642
(FLE_S_INX $rs1, $rs1)>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoM.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ let Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba] in {
112112
// inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish
113113
// zeroing the upper 32 bits.
114114
def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))),
115-
(MULHU (SLLI GPR:$rs1, 32), (SLLI GPR:$rs2, 32))>;
115+
(MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>;
116116
} // Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba]
117117

118118
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

Lines changed: 30 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -548,65 +548,66 @@ def : Pat<(add_non_imm12 sh3add_op:$rs1, (XLenVT GPR:$rs2)),
548548
(TH_ADDSL GPR:$rs2, sh3add_op:$rs1, 3)>;
549549

550550
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 6)), GPR:$rs2),
551-
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 1), 1)>;
551+
(TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 1)), 1)>;
552552
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 10)), GPR:$rs2),
553-
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 2), 1)>;
553+
(TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 2)), 1)>;
554554
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 18)), GPR:$rs2),
555-
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 3), 1)>;
555+
(TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 3)), 1)>;
556556
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 12)), GPR:$rs2),
557-
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 1), 2)>;
557+
(TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 1)), 2)>;
558558
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 20)), GPR:$rs2),
559-
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 2), 2)>;
559+
(TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 2)), 2)>;
560560
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 36)), GPR:$rs2),
561-
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 3), 2)>;
561+
(TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 3)), 2)>;
562562
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 24)), GPR:$rs2),
563-
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 1), 3)>;
563+
(TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 1)), 3)>;
564564
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 40)), GPR:$rs2),
565-
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 2), 3)>;
565+
(TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 2)), 3)>;
566566
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2),
567-
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 3), 3)>;
567+
(TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 3)), 3)>;
568568

569569
def : Pat<(add (XLenVT GPR:$r), CSImm12MulBy4:$i),
570-
(TH_ADDSL GPR:$r, (ADDI (XLenVT X0), (SimmShiftRightBy2XForm CSImm12MulBy4:$i)), 2)>;
570+
(TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), (SimmShiftRightBy2XForm CSImm12MulBy4:$i))), 2)>;
571571
def : Pat<(add (XLenVT GPR:$r), CSImm12MulBy8:$i),
572-
(TH_ADDSL GPR:$r, (ADDI (XLenVT X0), (SimmShiftRightBy3XForm CSImm12MulBy8:$i)), 3)>;
572+
(TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), (SimmShiftRightBy3XForm CSImm12MulBy8:$i))), 3)>;
573573

574574
def : Pat<(mul (XLenVT GPR:$r), C3LeftShift:$i),
575-
(SLLI (TH_ADDSL GPR:$r, GPR:$r, 1),
575+
(SLLI (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 1)),
576576
(TrailingZeros C3LeftShift:$i))>;
577577
def : Pat<(mul (XLenVT GPR:$r), C5LeftShift:$i),
578-
(SLLI (TH_ADDSL GPR:$r, GPR:$r, 2),
578+
(SLLI (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)),
579579
(TrailingZeros C5LeftShift:$i))>;
580580
def : Pat<(mul (XLenVT GPR:$r), C9LeftShift:$i),
581-
(SLLI (TH_ADDSL GPR:$r, GPR:$r, 3),
581+
(SLLI (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 3)),
582582
(TrailingZeros C9LeftShift:$i))>;
583583

584584
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 11)),
585-
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 2), 1)>;
585+
(TH_ADDSL GPR:$r, (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)), 1)>;
586586
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 19)),
587-
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 3), 1)>;
587+
(TH_ADDSL GPR:$r, (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 3)), 1)>;
588588
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 13)),
589-
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 1), 2)>;
589+
(TH_ADDSL GPR:$r, (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 1)), 2)>;
590590
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 21)),
591-
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 2), 2)>;
591+
(TH_ADDSL GPR:$r, (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)), 2)>;
592592
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 37)),
593-
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 3), 2)>;
593+
(TH_ADDSL GPR:$r, (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 3)), 2)>;
594594
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 25)),
595-
(TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 2), (TH_ADDSL GPR:$r, GPR:$r, 2), 2)>;
595+
(TH_ADDSL (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)),
596+
(XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)), 2)>;
596597
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 41)),
597-
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 2), 3)>;
598+
(TH_ADDSL GPR:$r, (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)), 3)>;
598599
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 73)),
599-
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 3), 3)>;
600+
(TH_ADDSL GPR:$r, (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 3)), 3)>;
600601
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 27)),
601-
(TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 3), (TH_ADDSL GPR:$r, GPR:$r, 3), 1)>;
602+
(TH_ADDSL (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 3)), (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 3)), 1)>;
602603
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 45)),
603-
(TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 3), (TH_ADDSL GPR:$r, GPR:$r, 3), 2)>;
604+
(TH_ADDSL (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 3)), (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 3)), 2)>;
604605
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 81)),
605-
(TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 3), (TH_ADDSL GPR:$r, GPR:$r, 3), 3)>;
606+
(TH_ADDSL (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 3)), (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 3)), 3)>;
606607

607608
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 200)),
608-
(SLLI (TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 2),
609-
(TH_ADDSL GPR:$r, GPR:$r, 2), 2), 3)>;
609+
(SLLI (XLenVT (TH_ADDSL (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)),
610+
(XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)), 2)), 3)>;
610611
} // Predicates = [HasVendorXTHeadBa]
611612

612613
let Predicates = [HasVendorXTHeadBb] in {
@@ -633,14 +634,14 @@ def : Pat<(sra (bswap i64:$rs1), (i64 32)),
633634
def : Pat<(binop_allwusers<srl> (bswap i64:$rs1), (i64 32)),
634635
(TH_REVW i64:$rs1)>;
635636
def : Pat<(riscv_clzw i64:$rs1),
636-
(TH_FF0 (SLLI (XORI i64:$rs1, -1), 32))>;
637+
(TH_FF0 (i64 (SLLI (i64 (XORI i64:$rs1, -1)), 32)))>;
637638
} // Predicates = [HasVendorXTHeadBb, IsRV64]
638639

639640
let Predicates = [HasVendorXTHeadBs] in {
640641
def : Pat<(and (srl (XLenVT GPR:$rs1), uimmlog2xlen:$shamt), 1),
641642
(TH_TST GPR:$rs1, uimmlog2xlen:$shamt)>;
642643
def : Pat<(XLenVT (seteq (and (XLenVT GPR:$rs1), SingleBitSetMask:$mask), 0)),
643-
(TH_TST (XORI GPR:$rs1, -1), SingleBitSetMask:$mask)>;
644+
(TH_TST (XLenVT (XORI GPR:$rs1, -1)), SingleBitSetMask:$mask)>;
644645
} // Predicates = [HasVendorXTHeadBs]
645646

646647
let Predicates = [HasVendorXTHeadCondMov] in {

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