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fix Matthew's comments, remove helper function of retRegStatus
1 parent d957df9 commit abf1428

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+36
-30
lines changed

1 file changed

+36
-30
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llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 36 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -4336,7 +4336,7 @@ enum class SrcStatus {
43364336
HALF_START = IS_UPPER_HALF,
43374337
HALF_END = IS_LOWER_HALF_NEG
43384338
};
4339-
4339+
// Test if the MI is truncating to half, such as `%reg0:n = G_TRUNC %reg1:2n`
43404340
static bool isTruncHalf(const MachineInstr *MI,
43414341
const MachineRegisterInfo &MRI) {
43424342
if (MI->getOpcode() != AMDGPU::G_TRUNC)
@@ -4347,6 +4347,8 @@ static bool isTruncHalf(const MachineInstr *MI,
43474347
return DstSize * 2 == SrcSize;
43484348
}
43494349

4350+
// Test if the MI is logic shift right with half bits,
4351+
// such as `%reg0:2n =G_LSHR %reg1:2n, CONST(n)`
43504352
static bool isLshrHalf(const MachineInstr *MI, const MachineRegisterInfo &MRI) {
43514353
if (MI->getOpcode() != AMDGPU::G_LSHR)
43524354
return false;
@@ -4362,6 +4364,8 @@ static bool isLshrHalf(const MachineInstr *MI, const MachineRegisterInfo &MRI) {
43624364
return false;
43634365
}
43644366

4367+
// Test if the MI is shift left with half bits,
4368+
// such as `%reg0:2n =G_SHL %reg1:2n, CONST(n)`
43654369
static bool isShlHalf(const MachineInstr *MI, const MachineRegisterInfo &MRI) {
43664370
if (MI->getOpcode() != AMDGPU::G_SHL)
43674371
return false;
@@ -4377,6 +4381,7 @@ static bool isShlHalf(const MachineInstr *MI, const MachineRegisterInfo &MRI) {
43774381
return false;
43784382
}
43794383

4384+
// Test function, if the MI is `%reg0:n, %reg1:n = G_UNMERGE_VALUES %reg2:2n`
43804385
static bool isUnmergeHalf(const MachineInstr *MI,
43814386
const MachineRegisterInfo &MRI) {
43824387
if (MI->getOpcode() != AMDGPU::G_UNMERGE_VALUES)
@@ -4385,15 +4390,6 @@ static bool isUnmergeHalf(const MachineInstr *MI,
43854390
MI->getOperand(1).isDef() && !MI->getOperand(2).isDef();
43864391
}
43874392

4388-
static std::optional<std::pair<Register, SrcStatus>>
4389-
retRegStat(Register Reg, SrcStatus Stat) {
4390-
if (Stat != SrcStatus::INVALID && !(Reg.isPhysical())) {
4391-
return std::optional<std::pair<Register, SrcStatus>>({Reg, Stat});
4392-
}
4393-
4394-
return std::nullopt;
4395-
}
4396-
43974393
enum class TypeClass { VECTOR_OF_TWO, SCALAR, NONE_OF_LISTED };
43984394

43994395
static TypeClass isVectorOfTwoOrScalar(Register Reg,
@@ -4571,10 +4567,17 @@ calcNextStatus(std::pair<Register, SrcStatus> Curr,
45714567
switch (Opc) {
45724568
case AMDGPU::G_BITCAST:
45734569
case AMDGPU::COPY:
4574-
return retRegStat(MI->getOperand(1).getReg(), Curr.second);
4575-
case AMDGPU::G_FNEG:
4576-
return retRegStat(MI->getOperand(1).getReg(),
4577-
getNegStatus(Curr.first, Curr.second, MRI));
4570+
if (MI->getOperand(1).getReg().isPhysical())
4571+
return std::nullopt;
4572+
return std::optional<std::pair<Register, SrcStatus>>(
4573+
{MI->getOperand(1).getReg(), Curr.second});
4574+
case AMDGPU::G_FNEG: {
4575+
SrcStatus Stat = getNegStatus(Curr.first, Curr.second, MRI);
4576+
if (Stat == SrcStatus::INVALID)
4577+
return std::nullopt;
4578+
return std::optional<std::pair<Register, SrcStatus>>(
4579+
{MI->getOperand(1).getReg(), Stat});
4580+
}
45784581
default:
45794582
break;
45804583
}
@@ -4583,11 +4586,11 @@ calcNextStatus(std::pair<Register, SrcStatus> Curr,
45834586
switch (Curr.second) {
45844587
case SrcStatus::IS_SAME:
45854588
if (isTruncHalf(MI, MRI))
4586-
return retRegStat(MI->getOperand(1).getReg(), SrcStatus::IS_LOWER_HALF);
4589+
return std::optional<std::pair<Register, SrcStatus>>({MI->getOperand(1).getReg(), SrcStatus::IS_LOWER_HALF});
45874590
else if (isUnmergeHalf(MI, MRI)) {
45884591
if (Curr.first == MI->getOperand(0).getReg())
4589-
return retRegStat(MI->getOperand(2).getReg(), SrcStatus::IS_LOWER_HALF);
4590-
return retRegStat(MI->getOperand(2).getReg(), SrcStatus::IS_UPPER_HALF);
4592+
return std::optional<std::pair<Register, SrcStatus>>({MI->getOperand(2).getReg(), SrcStatus::IS_LOWER_HALF});
4593+
return std::optional<std::pair<Register, SrcStatus>>({MI->getOperand(2).getReg(), SrcStatus::IS_UPPER_HALF});
45914594
}
45924595
break;
45934596
case SrcStatus::IS_HI_NEG:
@@ -4598,33 +4601,36 @@ calcNextStatus(std::pair<Register, SrcStatus> Curr,
45984601
// Src = [SrcHi, SrcLo] = [-CurrHi, CurrLo]
45994602
// = [-OpLowerHi, OpLowerLo]
46004603
// = -OpLower
4601-
return retRegStat(MI->getOperand(1).getReg(),
4602-
SrcStatus::IS_LOWER_HALF_NEG);
4603-
} else if (isUnmergeHalf(MI, MRI)) {
4604+
return std::optional<std::pair<Register, SrcStatus>>({MI->getOperand(1).getReg(),
4605+
SrcStatus::IS_LOWER_HALF_NEG});
4606+
}
4607+
if (isUnmergeHalf(MI, MRI)) {
46044608
if (Curr.first == MI->getOperand(0).getReg())
4605-
return retRegStat(MI->getOperand(2).getReg(),
4606-
SrcStatus::IS_LOWER_HALF_NEG);
4607-
return retRegStat(MI->getOperand(2).getReg(),
4608-
SrcStatus::IS_UPPER_HALF_NEG);
4609+
return std::optional<std::pair<Register, SrcStatus>>({MI->getOperand(2).getReg(),
4610+
SrcStatus::IS_LOWER_HALF_NEG});
4611+
return std::optional<std::pair<Register, SrcStatus>>({MI->getOperand(2).getReg(),
4612+
SrcStatus::IS_UPPER_HALF_NEG});
46094613
}
46104614
break;
46114615
case SrcStatus::IS_UPPER_HALF:
46124616
if (isShlHalf(MI, MRI))
4613-
return retRegStat(MI->getOperand(1).getReg(), SrcStatus::IS_LOWER_HALF);
4617+
return std::optional<std::pair<Register, SrcStatus>>(
4618+
{MI->getOperand(1).getReg(), SrcStatus::IS_LOWER_HALF});
46144619
break;
46154620
case SrcStatus::IS_LOWER_HALF:
46164621
if (isLshrHalf(MI, MRI))
4617-
return retRegStat(MI->getOperand(1).getReg(), SrcStatus::IS_UPPER_HALF);
4622+
return std::optional<std::pair<Register, SrcStatus>>(
4623+
{MI->getOperand(1).getReg(), SrcStatus::IS_UPPER_HALF});
46184624
break;
46194625
case SrcStatus::IS_UPPER_HALF_NEG:
46204626
if (isShlHalf(MI, MRI))
4621-
return retRegStat(MI->getOperand(1).getReg(),
4622-
SrcStatus::IS_LOWER_HALF_NEG);
4627+
return std::optional<std::pair<Register, SrcStatus>>(
4628+
{MI->getOperand(1).getReg(), SrcStatus::IS_LOWER_HALF_NEG});
46234629
break;
46244630
case SrcStatus::IS_LOWER_HALF_NEG:
46254631
if (isLshrHalf(MI, MRI))
4626-
return retRegStat(MI->getOperand(1).getReg(),
4627-
SrcStatus::IS_UPPER_HALF_NEG);
4632+
return std::optional<std::pair<Register, SrcStatus>>(
4633+
{MI->getOperand(1).getReg(), SrcStatus::IS_UPPER_HALF_NEG});
46284634
break;
46294635
default:
46304636
break;

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