@@ -4336,7 +4336,7 @@ enum class SrcStatus {
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HALF_START = IS_UPPER_HALF,
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HALF_END = IS_LOWER_HALF_NEG
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};
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-
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+ // Test if the MI is truncating to half, such as `%reg0:n = G_TRUNC %reg1:2n`
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static bool isTruncHalf (const MachineInstr *MI,
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const MachineRegisterInfo &MRI) {
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if (MI->getOpcode () != AMDGPU::G_TRUNC)
@@ -4347,6 +4347,8 @@ static bool isTruncHalf(const MachineInstr *MI,
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return DstSize * 2 == SrcSize;
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}
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+ // Test if the MI is logic shift right with half bits,
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+ // such as `%reg0:2n =G_LSHR %reg1:2n, CONST(n)`
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static bool isLshrHalf (const MachineInstr *MI, const MachineRegisterInfo &MRI) {
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if (MI->getOpcode () != AMDGPU::G_LSHR)
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return false ;
@@ -4362,6 +4364,8 @@ static bool isLshrHalf(const MachineInstr *MI, const MachineRegisterInfo &MRI) {
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return false ;
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}
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+ // Test if the MI is shift left with half bits,
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+ // such as `%reg0:2n =G_SHL %reg1:2n, CONST(n)`
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static bool isShlHalf (const MachineInstr *MI, const MachineRegisterInfo &MRI) {
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if (MI->getOpcode () != AMDGPU::G_SHL)
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return false ;
@@ -4377,6 +4381,7 @@ static bool isShlHalf(const MachineInstr *MI, const MachineRegisterInfo &MRI) {
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return false ;
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}
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+ // Test function, if the MI is `%reg0:n, %reg1:n = G_UNMERGE_VALUES %reg2:2n`
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static bool isUnmergeHalf (const MachineInstr *MI,
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const MachineRegisterInfo &MRI) {
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if (MI->getOpcode () != AMDGPU::G_UNMERGE_VALUES)
@@ -4385,15 +4390,6 @@ static bool isUnmergeHalf(const MachineInstr *MI,
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MI->getOperand (1 ).isDef () && !MI->getOperand (2 ).isDef ();
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}
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- static std::optional<std::pair<Register, SrcStatus>>
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- retRegStat (Register Reg, SrcStatus Stat) {
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- if (Stat != SrcStatus::INVALID && !(Reg.isPhysical ())) {
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- return std::optional<std::pair<Register, SrcStatus>>({Reg, Stat});
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- }
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-
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- return std::nullopt;
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- }
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-
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enum class TypeClass { VECTOR_OF_TWO, SCALAR, NONE_OF_LISTED };
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static TypeClass isVectorOfTwoOrScalar (Register Reg,
@@ -4571,10 +4567,17 @@ calcNextStatus(std::pair<Register, SrcStatus> Curr,
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switch (Opc) {
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case AMDGPU::G_BITCAST:
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case AMDGPU::COPY:
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- return retRegStat (MI->getOperand (1 ).getReg (), Curr.second );
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- case AMDGPU::G_FNEG:
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- return retRegStat (MI->getOperand (1 ).getReg (),
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- getNegStatus (Curr.first , Curr.second , MRI));
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+ if (MI->getOperand (1 ).getReg ().isPhysical ())
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+ return std::nullopt;
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+ return std::optional<std::pair<Register, SrcStatus>>(
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+ {MI->getOperand (1 ).getReg (), Curr.second });
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+ case AMDGPU::G_FNEG: {
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+ SrcStatus Stat = getNegStatus (Curr.first , Curr.second , MRI);
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+ if (Stat == SrcStatus::INVALID)
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+ return std::nullopt;
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+ return std::optional<std::pair<Register, SrcStatus>>(
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+ {MI->getOperand (1 ).getReg (), Stat});
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+ }
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default :
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break ;
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}
@@ -4583,11 +4586,11 @@ calcNextStatus(std::pair<Register, SrcStatus> Curr,
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switch (Curr.second ) {
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case SrcStatus::IS_SAME:
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if (isTruncHalf (MI, MRI))
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- return retRegStat ( MI->getOperand (1 ).getReg (), SrcStatus::IS_LOWER_HALF);
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+ return std::optional<std::pair<Register, SrcStatus>>({ MI->getOperand (1 ).getReg (), SrcStatus::IS_LOWER_HALF} );
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else if (isUnmergeHalf (MI, MRI)) {
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if (Curr.first == MI->getOperand (0 ).getReg ())
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- return retRegStat ( MI->getOperand (2 ).getReg (), SrcStatus::IS_LOWER_HALF);
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- return retRegStat ( MI->getOperand (2 ).getReg (), SrcStatus::IS_UPPER_HALF);
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+ return std::optional<std::pair<Register, SrcStatus>>({ MI->getOperand (2 ).getReg (), SrcStatus::IS_LOWER_HALF} );
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+ return std::optional<std::pair<Register, SrcStatus>>({ MI->getOperand (2 ).getReg (), SrcStatus::IS_UPPER_HALF} );
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}
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break ;
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case SrcStatus::IS_HI_NEG:
@@ -4598,33 +4601,36 @@ calcNextStatus(std::pair<Register, SrcStatus> Curr,
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// Src = [SrcHi, SrcLo] = [-CurrHi, CurrLo]
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// = [-OpLowerHi, OpLowerLo]
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// = -OpLower
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- return retRegStat (MI->getOperand (1 ).getReg (),
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- SrcStatus::IS_LOWER_HALF_NEG);
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- } else if (isUnmergeHalf (MI, MRI)) {
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+ return std::optional<std::pair<Register, SrcStatus>>({MI->getOperand (1 ).getReg (),
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+ SrcStatus::IS_LOWER_HALF_NEG});
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+ }
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+ if (isUnmergeHalf (MI, MRI)) {
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if (Curr.first == MI->getOperand (0 ).getReg ())
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- return retRegStat ( MI->getOperand (2 ).getReg (),
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- SrcStatus::IS_LOWER_HALF_NEG);
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- return retRegStat ( MI->getOperand (2 ).getReg (),
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- SrcStatus::IS_UPPER_HALF_NEG);
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+ return std::optional<std::pair<Register, SrcStatus>>({ MI->getOperand (2 ).getReg (),
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+ SrcStatus::IS_LOWER_HALF_NEG} );
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+ return std::optional<std::pair<Register, SrcStatus>>({ MI->getOperand (2 ).getReg (),
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+ SrcStatus::IS_UPPER_HALF_NEG} );
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}
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break ;
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case SrcStatus::IS_UPPER_HALF:
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if (isShlHalf (MI, MRI))
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- return retRegStat (MI->getOperand (1 ).getReg (), SrcStatus::IS_LOWER_HALF);
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+ return std::optional<std::pair<Register, SrcStatus>>(
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+ {MI->getOperand (1 ).getReg (), SrcStatus::IS_LOWER_HALF});
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break ;
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case SrcStatus::IS_LOWER_HALF:
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if (isLshrHalf (MI, MRI))
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- return retRegStat (MI->getOperand (1 ).getReg (), SrcStatus::IS_UPPER_HALF);
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+ return std::optional<std::pair<Register, SrcStatus>>(
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+ {MI->getOperand (1 ).getReg (), SrcStatus::IS_UPPER_HALF});
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break ;
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case SrcStatus::IS_UPPER_HALF_NEG:
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if (isShlHalf (MI, MRI))
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- return retRegStat (MI-> getOperand ( 1 ). getReg (),
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- SrcStatus::IS_LOWER_HALF_NEG);
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+ return std::optional<std::pair<Register, SrcStatus>>(
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+ {MI-> getOperand ( 1 ). getReg (), SrcStatus::IS_LOWER_HALF_NEG} );
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break ;
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case SrcStatus::IS_LOWER_HALF_NEG:
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if (isLshrHalf (MI, MRI))
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- return retRegStat (MI-> getOperand ( 1 ). getReg (),
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- SrcStatus::IS_UPPER_HALF_NEG);
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+ return std::optional<std::pair<Register, SrcStatus>>(
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+ {MI-> getOperand ( 1 ). getReg (), SrcStatus::IS_UPPER_HALF_NEG} );
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break ;
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default :
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break ;
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