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[RISCV] Rematerialize vid.v (#97520)
This adds initial support for rematerializing vector instructions, starting with vid.v since it's simple and has the least number of operands. It has one passthru operand which we need to check is undefined. It also has an AVL operand, but it's fine to rematerialize with it because it's scalar and register allocation is split between vector and scalar. RISCVInsertVSETVLI can still happen before vector regalloc if -riscv-vsetvl-after-rvv-regalloc is false, so this makes sure that we only rematerialize after regalloc by checking for the implicit uses that are added.
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

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@@ -166,6 +166,18 @@ Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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return 0;
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}
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bool RISCVInstrInfo::isReallyTriviallyReMaterializable(
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const MachineInstr &MI) const {
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if (RISCV::getRVVMCOpcode(MI.getOpcode()) == RISCV::VID_V &&
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MI.getOperand(1).isUndef() &&
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/* After RISCVInsertVSETVLI most pseudos will have implicit uses on vl and
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vtype. Make sure we only rematerialize before RISCVInsertVSETVLI
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i.e. -riscv-vsetvl-after-rvv-regalloc=true */
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!MI.hasRegisterImplicitUseOperand(RISCV::VTYPE))
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return true;
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return TargetInstrInfo::isReallyTriviallyReMaterializable(MI);
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}
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static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg,
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unsigned NumRegs) {
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return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.h

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@@ -76,6 +76,8 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
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Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
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unsigned &MemBytes) const override;
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bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
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void copyPhysRegVector(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
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MCRegister DstReg, MCRegister SrcReg, bool KillSrc,

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

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@@ -6629,6 +6629,7 @@ defm PseudoVIOTA_M: VPseudoVIOTA_M;
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//===----------------------------------------------------------------------===//
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// 15.9. Vector Element Index Instruction
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//===----------------------------------------------------------------------===//
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let isReMaterializable = 1 in
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defm PseudoVID : VPseudoVID_V;
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} // Predicates = [HasVInstructions]
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‎llvm/test/CodeGen/RISCV/rvv/remat.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,POSTRA
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-vsetvl-after-rvv-regalloc=false -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,PRERA
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define void @vid(ptr %p) {
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; POSTRA-LABEL: vid:
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; POSTRA: # %bb.0:
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; POSTRA-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; POSTRA-NEXT: vid.v v8
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; POSTRA-NEXT: vs8r.v v8, (a0)
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; POSTRA-NEXT: vl8re64.v v16, (a0)
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; POSTRA-NEXT: vl8re64.v v24, (a0)
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; POSTRA-NEXT: vl8re64.v v0, (a0)
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; POSTRA-NEXT: vl8re64.v v8, (a0)
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; POSTRA-NEXT: vs8r.v v8, (a0)
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; POSTRA-NEXT: vs8r.v v0, (a0)
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; POSTRA-NEXT: vs8r.v v24, (a0)
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; POSTRA-NEXT: vs8r.v v16, (a0)
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; POSTRA-NEXT: vid.v v8
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; POSTRA-NEXT: vs8r.v v8, (a0)
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; POSTRA-NEXT: ret
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;
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; PRERA-LABEL: vid:
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; PRERA: # %bb.0:
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; PRERA-NEXT: addi sp, sp, -16
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; PRERA-NEXT: .cfi_def_cfa_offset 16
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; PRERA-NEXT: csrr a1, vlenb
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; PRERA-NEXT: slli a1, a1, 3
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; PRERA-NEXT: sub sp, sp, a1
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; PRERA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
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; PRERA-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; PRERA-NEXT: vid.v v8
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; PRERA-NEXT: vs8r.v v8, (a0)
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; PRERA-NEXT: vl8re64.v v16, (a0)
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; PRERA-NEXT: addi a1, sp, 16
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; PRERA-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
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; PRERA-NEXT: vl8re64.v v24, (a0)
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; PRERA-NEXT: vl8re64.v v0, (a0)
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; PRERA-NEXT: vl8re64.v v16, (a0)
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; PRERA-NEXT: vs8r.v v16, (a0)
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; PRERA-NEXT: vs8r.v v0, (a0)
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; PRERA-NEXT: vs8r.v v24, (a0)
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; PRERA-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
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; PRERA-NEXT: vs8r.v v16, (a0)
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; PRERA-NEXT: vs8r.v v8, (a0)
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; PRERA-NEXT: csrr a0, vlenb
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; PRERA-NEXT: slli a0, a0, 3
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; PRERA-NEXT: add sp, sp, a0
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; PRERA-NEXT: addi sp, sp, 16
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; PRERA-NEXT: ret
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%vid = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(<vscale x 8 x i64> poison, i64 -1)
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store volatile <vscale x 8 x i64> %vid, ptr %p
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%a = load volatile <vscale x 8 x i64>, ptr %p
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%b = load volatile <vscale x 8 x i64>, ptr %p
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%c = load volatile <vscale x 8 x i64>, ptr %p
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%d = load volatile <vscale x 8 x i64>, ptr %p
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store volatile <vscale x 8 x i64> %d, ptr %p
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store volatile <vscale x 8 x i64> %c, ptr %p
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store volatile <vscale x 8 x i64> %b, ptr %p
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store volatile <vscale x 8 x i64> %a, ptr %p
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store volatile <vscale x 8 x i64> %vid, ptr %p
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ret void
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}
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define void @vid_passthru(ptr %p, <vscale x 8 x i64> %v) {
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; CHECK-LABEL: vid_passthru:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
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; CHECK-NEXT: vsetivli zero, 1, e64, m8, tu, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: addi a1, sp, 16
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; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
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; CHECK-NEXT: vl8re64.v v24, (a0)
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; CHECK-NEXT: vl8re64.v v0, (a0)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vs8r.v v0, (a0)
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; CHECK-NEXT: vs8r.v v24, (a0)
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; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
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; CHECK-NEXT: vs8r.v v16, (a0)
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; CHECK-NEXT: vs8r.v v8, (a0)
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%vid = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(<vscale x 8 x i64> %v, i64 1)
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store volatile <vscale x 8 x i64> %vid, ptr %p
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%a = load volatile <vscale x 8 x i64>, ptr %p
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%b = load volatile <vscale x 8 x i64>, ptr %p
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%c = load volatile <vscale x 8 x i64>, ptr %p
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%d = load volatile <vscale x 8 x i64>, ptr %p
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store volatile <vscale x 8 x i64> %d, ptr %p
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store volatile <vscale x 8 x i64> %c, ptr %p
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store volatile <vscale x 8 x i64> %b, ptr %p
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store volatile <vscale x 8 x i64> %a, ptr %p
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store volatile <vscale x 8 x i64> %vid, ptr %p
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ret void
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}

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